Abstract: A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or “fuse” which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.

Abstract: A bond pad structure is provided which has a primary bond pad region electrically connected to a secondary bond pad region. The secondary bond pad region is used to test a circuit for configuration, while the primary bond pad is covered with a protective oxide. After configuration and etching to complete desired disconnections, the oxide is removed from the primary bond pad region, leaving an undamaged surface for subsequent wire bonding. The primary bond pad region and the secondary bond pad region can be a unitary structure or two separate structures.

Abstract: A bond pad structure is provided which has a primary bond pad region electrically connected to a secondary bond pad region. The secondary bond pad region is used to test a circuit for configuration, while the primary bond pad is covered with a protective oxide. After configuration and etching to complete desired disconnections, the oxide is removed from the primary bond pad region, leaving an undamaged surface for subsequent wire bonding. The primary bond pad region and the secondary bond pad region can be a unitary structure or two separate structures.

Abstract: Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device.

Abstract: An unprogrammed die is attached to a die package, and bond wires are attached between the die and lead fingers on the die package. A cavity in the die package allows the die to be configured, such as with a laser. The die is then tested and, if needed, etched to ensure the desired configuration. The die package is sealed, such as with a filler material or a lid to protect the configured die and bond wires. In one embodiment, the die and bond wires are fully exposed through the cavity. In another embodiment, only a minority portion of the bona wires are exposed through the cavity. The cavity can be formed either prior to or after attaching the die and bond wires to the die package.

Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: A process for packaging a die uses compressible microspheres to form a stress buffer layer between the die and an epoxy encapsulant to absorb stresses on the die caused by the different thermal expansion rates of the epoxy and die during temperature changes. By using a compressible layer of microspheres or other material, the need for a nitride passivation or other insulating layer to protect the die from thermally-induced stress is eliminated. In addition, the number and size of the microspheres and the amount of epoxy used to seal the package can be adjusted so that the epoxy is approximately co-planar with the top of the package to allow the package to be handled and used with standard equipment and processes.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the desired connections, vias or cut-points for customization.Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: A process for packaging a die uses compressible microspheres to form a stress buffer layer between the die and an epoxy encapsulant to absorb stresses on the die caused by the different thermal expansion rates of the epoxy and die during temperature changes. By using a compressible layer of microspheres or other material, the need for a nitride passivation or other insulating layer to protect the die from thermally-induced stress is eliminated. In addition, the number and size of the microspheres and the amount of epoxy used to seal the package can be adjusted so that the epoxy is approximately co-planar with the top of the package to allow the package to be handled and used with standard equipment and processes.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations on a second photoresist layer, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: A method is provided for making re-usable configuration masks by initially patterning a mask blank using precision mask-making tools. The mask is then covered with an opaque material, and desired configuration points for a particular ASIC are selected with a non-precision laser. After the particular configuration pattern is no longer needed, the remaining opaque material is removed. The mask can then be re-configured for a new design by covering the mask with a new layer of opaque material and selecting new configuration points. Such a mask reduces both time and costs for creating a set of mask designs because a single mask can be re-used for several different designs without the further need of precision mask-making tools.

Abstract: A ceramic spinneret used for producing manufactured fibers and formed from a fine grained, essentially pure structural ceramic such as aluminum oxide, zirconium oxide, composites of aluminum oxide and zirconium oxide known as toughed ceramics, silicon nitride, silicon carbide, or any fine grained essentially pure structural ceramic. Such spinnerets are formed as a single piece and contain non-circular capillaries suitable for forming shaped or void containing fibers.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.

Abstract: An apparatus for measuring the gripping strength of a wafer holder, such as a vacuum wand or an automated robotic arm, is used to periodically test wafer holders during manufacture of wafers, and thereby eliminate the damage caused to wafers by worn wafer holders. The apparatus includes a hold tester to be held by the wafer holder and a gauge coupled to the hold tester that indicates the force applied by the wafer holder to the hold tester. The wafer holder is coupled to a predetermined region on the hold tester, and the wafer holder gauge is pulled away from the hold tester until the wafer holder becomes separated from the hold tester. The maximum force applied by the wafer holder on the hold tester is measured by the gauge and the above described process is repeated to obtain a second measurement of the force.

Abstract: A support arm is adapted for high-speed positioning of a transducer such as a read/write head in a magnetic disk drive. The support arm is essentially composed of a ceramic material having a high specific stiffness. The support arm is shaped to form structures integral of the support arm for mating with fasteners for connecting a transducer assembly to one end of the support arm and for connecting the support arm to a positioning actuator.