Patents by Inventor John A. Ott

John A. Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6903598
    Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventors: Martin Spence Denham, Mohsen Alavi, Kaizad Rumy Mistry, Patrick John Ott, Rachael Jade Parker, Paul Gregory Slankard, Wenliang Chen
  • Publication number: 20050116290
    Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 2, 2005
    Inventors: Joel de Souza, John Ott, Alexander Reznicek, Katherine Saenger
  • Patent number: 6858502
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: February 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Publication number: 20040227154
    Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1-yGey, within a relaxed Si1-xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.
    Type: Application
    Filed: April 26, 2004
    Publication date: November 18, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Publication number: 20040079890
    Abstract: There is disclosed a device for imaging radionuclide emissions comprising: a charge coupled device or CMOS active pixel sensor device; and a scintillator layer in direct contact with the charge coupled device or CMOS active pixel sensor device; in which the thickness of the scintillator layer is greater than 200 &mgr;m, preferably greater than 400 &mgr;m, most preferably about 500 &mgr;m.
    Type: Application
    Filed: December 1, 2003
    Publication date: April 29, 2004
    Inventors: George William Fraser, Robert John Ott, John Ernest Wyper Lees
  • Publication number: 20030218492
    Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.
    Type: Application
    Filed: May 24, 2002
    Publication date: November 27, 2003
    Applicant: Intel Corporation
    Inventors: Martin Spence Denham, Mohsen Alavi, Kaizad Rumy Mistry, Patrick John Ott, Rachael Jade Parker, Paul Gregory Slankard, Wenliang Chen
  • Publication number: 20030139000
    Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.
    Type: Application
    Filed: January 23, 2002
    Publication date: July 24, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Jack O. Chu, Keith E. Fogel, Steven J. Koester, Devendra K. Sadana, John A OTT
  • Publication number: 20020125475
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Application
    Filed: November 20, 2001
    Publication date: September 12, 2002
    Inventors: Jack Oon Chu, Richard Hammond, Khalid Ezzeldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Patent number: 6350993
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: February 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott