Abstract: An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the generated memory requests may be received out-of-order. An instruction scheduler in the on-chip cache stores pending received memory requests and effects the re-ordering by selecting a sequence of pending memory requests for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is returned. The memory requests which are received may be received from another, lower level on-chip cache or from registers.

Abstract: A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addr

Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Abstract: The present invention relates to a cyclic peptide, a conjugate comprising said cyclic peptide and a lipopeptide building block, a bundle of said conjugates, a synthetic virus-like particle comprising at least one bundle of conjugates and pharmaceutical compositions comprising the same. The present invention further relates to said cyclic peptide, said conjugate said bundle of conjugates, said synthetic virus-like particle and said pharmaceutical compositions for use as a medicament, preferably for use in a method for preventing of an infectious disease or reducing the risk of an infectious disease, more preferably for use in a method for preventing or reducing the risk of an infectious disease associated with or caused by a respiratory syncytial virus.

Abstract: This application describes compounds, compositions, and methods which are useful in treating, preventing, inhibiting, ameliorating, or eradicating the pathology and/or symptomology of a disease caused by a parasite.

Abstract: A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addr

Abstract: An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the generated memory requests may be received out-of-order. An instruction scheduler in the on-chip cache stores pending received memory requests and effects the re-ordering by selecting a sequence of pending memory requests for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is returned. The memory requests which are received may be received from another, lower level on-chip cache or from registers.

Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Abstract: The present invention relates to shaker doors with solid cores and methods for making the same. The shaker doors contain different core materials at the recessed panel than the raise peripheral region to provide dimensional stability and reduced distortion when the doors are exposed to high humidity. The devices and methods also provide for easy assembly of solid core shaker doors, including fire rated doors.

Abstract: The invention is a method and device for normalizing communication. The method includes receiving on a first device a first message via a first protocol from a second device; transmitting a second message to a third device via a second protocol, wherein the second message is transmitted using a first spreading factor; initiating a delay timer upon transmitting the second message, wherein a duration of the delay timer is based on a second spreading factor, wherein the second spreading factor is greater than or equal to the first spreading factor; receiving a third message from the third device via the second protocol, wherein the third message is transmitted using the first spreading factor, and wherein the third message is in response to the second message; and upon the expiration of the delay timer, sending a fourth message to the second device via the first protocol. The device includes the hardware and instructions to perform the method.

Abstract: A speech processing system includes an input for receiving an input utterance spoken by a user and a word alignment unit configured to align different sequences of acoustic speech models with the input utterance spoken by the user. Each different sequence of acoustic speech models corresponds to a different possible utterance that a user might make. The system identifies any parts of a read prompt text that the user skipped; any parts of the read prompt text that the user repeated; and any speech sounds that the user inserted between words of the read prompt text. The information from the word alignment unit can be used to assess the proficiency and/or fluency of the user's speech.

Abstract: A speech processing system includes an input for receiving an input utterance spoken by a user and a word alignment unit configured to align different sequences of acoustic speech models with the input utterance spoken by the user. Each different sequence of acoustic speech models corresponds to a different possible utterance that a user might make. The system identifies any parts of a read prompt text that the user skipped; any parts of the read prompt text that the user repeated; and any speech sounds that the user inserted between words of the read prompt text. The information from the word alignment unit can be used to assess the proficiency and/or fluency of the user's speech.

Abstract: The present invention relates to shaker doors with solid cores and methods for making the same. The shaker doors contain different core materials at the recessed panel than the raise peripheral region to provide dimensional stability and reduced distortion when the doors are exposed to high humidity. The devices and methods also provide for easy assembly of solid core shaker doors, including fire rated doors.

Abstract: A processing apparatus includes a microwave processing chamber. In addition, the processing apparatus includes a rigid, rotatable feed wheel rotatable about an axis of rotation such that a part of the feed wheel is located within the processing chamber. Further, the processing apparatus includes a feed device configured to deposit materials to be processed onto the feed wheel. Still further, the processing apparatus includes an output into which processed materials from the feed wheel can be deposited.

Abstract: A wafer carrier purge apparatus, an automated mechanical handling system, and a method of handling a wafer carrier during integrated circuit fabrication are provided. The wafer carrier purge apparatus includes a purge plate adapted for insertion into a carrier storage position. The purge plate includes a gas port and a gas nozzle in fluid communication with the gas port. The gas port receives a gas flow. The gas nozzle is adapted to contact an inlet port of a wafer carrier. The purge plate further includes a vacuum port and a vacuum nozzle in fluid communication with the vacuum port, spaced from the gas nozzle. The vacuum nozzle is adapted to capture gas that escapes from the wafer carrier through an outlet port of the wafer carrier. The purge plate is separate and removable from the carrier storage position.

Abstract: A time-temperature integrating (TTi) indicator label comprises an initiator reservoir and a target reservoir, said initiator reservoir containing a pH modification system and said target reservoir comprising a pH responsive indicator. The pH responsive indicator may be photo-initiated. There is also provided a time-temperature indicator label comprising first and second reservoirs separated by a hydrogel valve, said valve allowing passage of an acid from said first reservoir to said second reservoir when the hydrogel valve is activated.

Abstract: Disclosed herein are wireless devices operable at intermediate wireless at ranges of thousands of meters, utilizing packets that include a preamble and a data payload. Devices may be such things as keypads, door latches, occupancy monitors, sprinkler controllers and other devices needing a communications link. Devices include an intermediate-range transceiver and a separate deployment wireless interface accessible from a mobile device such as a cellular telephone or portable tablet. Devices can be registered in a database and deployed for use by means of an application running on the mobile device. A scannable label bearing a code can be affixed to a wireless device providing a means of tracking, identifying and verifying a device through the deployment process. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.

Abstract: An apparatus for distributing data using a short-range wireless interconnection protocol for electronic devices includes a processor communicatively connected, using a communication bus, to a number of originator antennas, each of the number of originator antennas communicating with an originating device, a plurality of device antennas, communicatively connected to the communication bus, each of the plurality of device antennas communicating with a number of client devices, and a non-transitory storage medium. The non-transitory storage medium includes a receive module, a session identify module, and a send module. The receive module receives a data packet using one of the number of originator antennas. The session identify module identifies at least one communication session with at least one remote device associated with one of the plurality of device antennas. The send module sends the data packet to the at least one remote device associated with one of the plurality of device antennas.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: A refrigerant compressor according to an exemplary aspect of the present disclosure includes, among other things, a first compression stage arranged in a main refrigerant flow path. The first compression stage is a mixed compression stage having both axial and radial components. The compressor further includes a second compression stage arranged in the main refrigerant flow path downstream of the first compression stage. The second compression stage is a radial compression stage.