Abstract: A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

Abstract: A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.

Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.

Abstract: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.

Abstract: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.

Abstract: A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.

Abstract: A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.

Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

Abstract: A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.

Abstract: A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.

Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

Abstract: A system is presented providing content to a plurality of handheld devices (including musical selections). The devices can access a server over the Internet via a Wi-Fi or other similar wireless interconnection and can download songs requested by a user from the server or from other users using, e.g., a P2P protocol. All downloads may be governed by applicable DRM rules. Content and playlists may also be pushed by a server from other sources and means including, e.g., podcasting, based on predetermined rules, favorite preferences of users, and other criteria.

Abstract: A method, structures and computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A method, apparatus and computer program product are provided for implementing high frequency return current paths utilizing decoupling capacitors within electronic packages. Electronic package physical design data are received for identifying a board layout. For each of a plurality of cells in a grid of a set cell size within the identified board layout, a respective number of signal vias are identified. A ratio of signal vias to return current paths is calculated for each of the plurality of cells. Each cell having a calculated ratio greater than a target ratio is identified. One or more decoupling capacitors are selectively added within each of the identified cells to provide high frequency return current paths.

Abstract: A method of testing and an embedded probe-enabling socket are provided for implementing debug and testing functions. The socket includes an integral probe structure enabling Top Side of the Module (TSM) signal probing. The socket includes a substrate with a topside including a plurality of probe pads. A TSM socket frame includes a plurality of probe pins electrically connecting to respective probe pads on the substrate topside. The probe pins are electrically connected with a respective signal to be monitored.

Abstract: An improved method and apparatus for packaging perishable goods comprises an inner insulating container that is quickly and easily formed from a flat sheet of metalized bubble pack material to a finished state that very closely approximates the size and dimensions of the carton. The constructed inner container can be quickly collapsed and reconstructed to improve the stackability and diminish the amount of space required to store the containers prior to use.

Abstract: A portable radiation detector using a high-purity germanium crystal as the sensing device. The crystal is fabricated such that it exhibits a length to width ratio greater than 1:1 and is oriented within the detector to receive radiation along the width of said crystal. The crystal is located within a container pressurized with ultra-pure nitrogen, and the container is located within a cryostat under vacuum.

Abstract: A system for air injection into tires, comprising a rotary air chamber secured to a hub cap wherein the rotary air chamber is configured to inject air into at least one tire when tire pressure drops below a first adjustable preset value and to release air from the at least one tire when tire pressure rises above a second adjustable preset value, an air shaft extending through the hub cap and into the rotary air chamber, an air line attached to the air shaft, and ball bearings affixed between the air shaft and the hub cap. A bracket can be fastened to the hub cap such that the rotary air chamber is fastened to the bracket. The hub cap and air shaft are fastened to the axle such that an air line extends from inside the axle through the air shaft to the rotary air chamber.

Abstract: A method and stiffener-embedded waveguide structure are provided for implementing enhanced data transfer for printed circuit board applications. At least one microwave channel is defined within a stiffener. The microwave channel provides a high frequency path for data transfers. Use of the waveguide channel in the stiffener for data transfers can replace or supplement otherwise required transmission paths in an associated printed circuit board.

Abstract: A method and structure are provided to control common mode impedance in fan-out regions for printed circuit board applications. A differential pair transmission line includes a narrow signal trace portion in the fan-out region and a wider signal trace portion outside of the fan-out region. A dielectric material separates the differential pair transmission line from a reference power plane. A thickness of the narrow signal trace is increased and a thickness of the dielectric material is correspondingly decreased in the fan-out region.