Abstract: Systems and methods applicable, for instance, to using continuous levels of detail (CLODs) in connection with computer graphic models. Distinct levels of detail (LODs) can be generated, floating point LOD (fLOD) values can be calculated, and interpolated LODs can be generated. Further, LOD display can occur.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: A diesel engine piston has a body and a crown engaged to the body with three inertially welded struts. The body includes a base extending downward opposite the crown with pin bosses having pin bores and a skirt extending downward from the base.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: Systems and methods applicable, for instance, to using continuous levels of detail (CLODs) in connection with computer graphic models. Distinct levels of detail (LODs) can be generated, floating point LOD (fLOD) values can be calculated, and interpolated LODs can be generated. Further, LOD display can occur.

Abstract: A diesel engine piston has a body and a crown engaged to the body with three inertially welded struts. The body includes a base extending downward opposite the crown with pin bosses having pin bores and a skirt extending downward from the base.

Abstract: Various embodiments include an on-die error correction code (ECC) system that preserves rectangular symbols of arbitrary size and shape, where the dimensions of the symbol are powers of two. Further, the on-die ECC system preserves symbols that include multiple rectangles of arbitrary size and shape, where the dimensions of each rectangle are powers of two, and where the vertical and horizontal offset between consecutive rectangles are also powers of two. If the on-die ECC system miscorrects a memory bit, then the miscorrection is constrained or restricted to the same symbol that includes the other error bits. Therefore, all error bits, including the miscorrected bit, are in the same symbol. As a result, a user ECC system, such as a symbol-based ECC system, can correct and detect any number of errors within a single symbol, even when the on-die ECC system miscorrects a memory bit.

Abstract: Various embodiments include an on-die error correction code (ECC) system that preserves rectangular symbols of arbitrary size and shape, where the dimensions of the symbol are powers of two. Further, the on-die ECC system preserves symbols that include multiple rectangles of arbitrary size and shape, where the dimensions of each rectangle are powers of two, and where the vertical and horizontal offset between consecutive rectangles are also powers of two. If the on-die ECC system miscorrects a memory bit, then the miscorrection is constrained or restricted to the same symbol that includes the other error bits. Therefore, all error bits, including the miscorrected bit, are in the same symbol. As a result, a user ECC system, such as a symbol-based ECC system, can correct and detect any number of errors within a single symbol, even when the on-die ECC system miscorrects a memory bit.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: A precise electrical current monitor having individual, communicatively coupled sensors providing separate readings to a processor. The monitor uses efficient switching logic requiring a single input to iteratively receive individual sensor readings from each sensor of the monitoring system. The monitor compensates for temperature effects on the sensor readings. The monitoring system is scalable depending on loads, circuits, appliances, or conductors through which the current being monitored flows. The monitoring system provides a continuous stream of data, including backed-up data when communications are down.

Abstract: The bag in box packaging comprising an inner bag, an outer carton and an inner spout retaining member. The inner bag defines a cavity with a spout coupled thereto. The outer carton includes a front wall and a first sidewall positioned adjacent the front wall, both extending from a bottom wall to a top wall. The inner spout retaining member including a first panel spanning diagonally from the first sidewall to the front wall obliquely relative to each wall and spaced apart from a side edge joining the front wall to the first sidewall, to define a triangular cross-sectional configuration. The first panel includes a spout retaining slot extending thereinto. The spout extends into the spout receiving slot so as to capture the spout within the cross-sectional configuration and directed toward the side edge. The inner bag is positioned on the opposite side of the first panel.

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract: There is a closure 1, which is, in this case, shown as closing a mouth 2 of a bottle 3, wherein the bottle is made of glass and has an external outwardly extending integral collar 4 which extends fully around an outside of the neck of the bottle and is of a constant shape and size at any location around the periphery. The seal 5 is held under compression against an uppermost rim 6 of the bottle mouth 2 and surface 7, which is adapted to engage with compression force the seal 5. Upon extraction of portion 8 from within the mouth of the bottle, a “popping” sound is achieved by having the position of the seal somewhat below the mouth prior to extraction so that there will be upon extraction an evacuation of the headspace within the bottle.

Abstract: A bag in box packaging including a flexible bag and an outer carton. The flexible bag defines a cavity, with a spout coupled thereto providing access to the cavity. The outer carton has a first sidewall and a second sidewall opposite the first side wall. A front wall extends therebetween. The inner spout retaining member further includes an inner spout retaining member. The inner spout retaining member includes a first panel that extends between the first sidewall and the second sidewall and is spaced apart from the front wall. The first panel includes a spout receiving slot extending thereinto. The spout of the bag is positionable within the spout receiving slot of the first panel, so as to position the spout between the first panel and the front wall. A spout locking member is structurally configured to maintain the spout within the spout receiving slot of the first panel.

Abstract: A bag-in-box assembly apparatus comprising a frame, an insertion assembly and assembly urging arms. The bag-in-box assembly apparatus is configured for use in association with a bag-in-box package having a box with an opening and a bag having a spout. A collar is coupled to the spout of the bag and the also interfaces with the opening of the box. The assembly apparatus is utilized to couple the collar to the bag, inserting the bag into the box and coupling the collar to the box.

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract: A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.