Patents by Inventor John C. Malinowski
John C. Malinowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079371Abstract: The present disclosure relates to radio frequency (RF) chip packages and, more particularly, to improved thermal performance of RF chip packages and methods of manufacture. The structure includes: a board; a chip substrate; a pattern of solder bumps between the board and the chip substrate; and a thermal conductive material between the chip substrate and the board in depopulated regions of solder bumps of the chip substrate.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: John C. MALINOWSKI, Zhuojie WU
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Patent number: 9287345Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.Type: GrantFiled: August 29, 2013Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, John C. Malinowski, Anthony K. Stamper
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Patent number: 9230921Abstract: A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack.Type: GrantFiled: October 8, 2013Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Stephen P. Ayotte, Alissa R. Cote, Kendra A. Lyons, John C. Malinowski, Benjamin J. Pierce
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Publication number: 20150097271Abstract: A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen P. Ayotte, Alissa R. Cote, Kendra A. Lyons, John C. Malinowski, Benjamin J. Pierce
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Patent number: 8729664Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.Type: GrantFiled: April 2, 2012Date of Patent: May 20, 2014Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
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Publication number: 20140001599Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen CHEN, Jeffrey P. GAMBINO, Zhong-Xiang HE, Tom C. LEE, John C. MALINOWSKI, Anthony K. STAMPER
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Patent number: 8563336Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.Type: GrantFiled: December 23, 2008Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, John C. Malinowski, Anthony K. Stamper
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Patent number: 8565510Abstract: Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: GrantFiled: January 27, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Publication number: 20130256826Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.Type: ApplicationFiled: April 2, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
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Patent number: 8299609Abstract: Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: GrantFiled: January 27, 2012Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Patent number: 8187897Abstract: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: GrantFiled: August 19, 2008Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Publication number: 20120120758Abstract: Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: ApplicationFiled: January 27, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Publication number: 20120119333Abstract: Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: ApplicationFiled: January 27, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Publication number: 20100155893Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen CHEN, Jeffrey P. GAMBINO, Zhong-Xiang HE, Tom C. LEE, John C. MALINOWSKI, Anthony K. STAMPER
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Publication number: 20100044858Abstract: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
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Patent number: 7067914Abstract: Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.Type: GrantFiled: November 9, 2001Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: John C. Malinowski, Edmund J. Sprogis, Steven H. Voldman
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Patent number: 7053460Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.Type: GrantFiled: December 21, 2001Date of Patent: May 30, 2006Assignee: International Business Machines CorporationInventors: Richard P. Volant, Seshadri Subbanna, Robert A. Groves, John C. Malinowski, Kenneth J. Stein, Kevin S. Petrarca
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Patent number: 7025891Abstract: A method of treating a molybdenum (moly) mask used in a C4 process to pattern C4 contacts. The moly mask has a wafer side which contacts a wafer during the C4 process and has a rough surface that includes spikes/projections of moly. The moly mask also has a non wafer side and a plurality of holes extending through the mask to pattern C4 contacts in the C4 process. An adhesive layer, such as an adhesive tape, is applied to the non wafer side of the moly mask, to enable a polishing tool to pull a vacuum on the non wafer side of the moly mask in spite of the presence of the holes to secure the moly mask during a subsequent polishing step. The tape also functions as a cushion so that defects on the non wafer side of the moly mask do not replicate through the moly mask to the polished wafer side of the moly mask.Type: GrantFiled: August 29, 2003Date of Patent: April 11, 2006Assignee: International Business Machines CorporationInventors: Steven R. Codding, Timothy C. Krywanczyk, Joseph D. Danaher, John C. Malinowski, James R. Palmer, Melvin T. Kelly, Caitlin W. Weinstein, Wolfgang Sauter
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Patent number: 6656375Abstract: An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.Type: GrantFiled: January 28, 1998Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Michael D. Armacost, David M. Dobuzinsky, John C. Malinowski, Hung Y. Ng, Richard S. Wise, Chienfan Yu
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Patent number: 6656815Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.Type: GrantFiled: April 4, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, John C. Malinowski