Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

Abstract: Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.

Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

Abstract: A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area.A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposited. This provides the ONO stack. Then a layer of polysilicon, a layer of nitride, and a layer of large-grained polysilicon are deposited sequentially. Then, a trench is defined by a lithographic mask and the exposed large-grained polysilicon is etched in CF.sub.4. Since CF.sub.4 etches the polysilicon and nitride 20 at almost the same rates, the topographical features existed in the polysilicon layer is copied to the nitride layer. The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF.sub.4, Helium, and NF.sub.3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide.