Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean begins with an initial plasma. A first physical signal is measured while the initial plasma is in progress, and the measured value is stored in a memory unit. A process controller retrieves the measured value, uses it to compute a deposition estimate parameter, and determines when the deposition estimate parameter meets a minimum deposition criterion. When the result of the determination is TRUE, the smart in-situ chamber clean terminates without an in-situ cleaning of the process chamber. When the result of the determination is FALSE, the smart in-situ chamber clean proceeds with an in-situ cleaning. The in-situ cleaning may be a continuation of the initial plasma. Subsequently, the microelectronic device is processed in the fabrication tool.

Abstract: A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean begins with an initial plasma. A first physical signal is measured while the initial plasma is in progress, and the measured value is stored in a memory unit. A process controller retrieves the measured value, uses it to compute a deposition estimate parameter, and determines when the deposition estimate parameter meets a minimum deposition criterion. When the result of the determination is TRUE, the smart in-situ chamber clean terminates without an in-situ cleaning of the process chamber. When the result of the determination is FALSE, the smart in-situ chamber clean proceeds with an in-situ cleaning. The in-situ cleaning may be a continuation of the initial plasma. Subsequently, the microelectronic device is processed in the fabrication tool.

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract: A plasma etch tool includes a wafer chuck with a chuck base and at least one functional component layer attached to the chuck base. A perimeter of the functional component layer has a polymer material permanently attached to it that extends to within 2 millimeters of a top surface of the chuck. The top surface of the wafer chuck contacts a bottom surface of a semiconductor wafer during an etch process for forming an integrated circuit. The polymer material is protected from an etch ambient by a plasma etcher chuck band installed around the perimeter of the functional component layer, extending over a portion of the chuck base. An integrated circuit may be formed by installing the plasma etcher chuck band on the chuck of the plasma etch tool, and subsequently performing an etch process in the plasma etch tool on a semiconductor wafer containing the partially formed integrated circuit.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: A baffle plate for redirecting a reactive gas flow within a process chamber of a semiconductor plasma processing apparatus includes a topside surface having a plurality of topside apertures for receiving the reactive gas flow and a bottomside surface having a plurality of bottomside apertures for emitting the reactive gas flow toward a semiconductor substrate. An outer portion of the baffle plate includes both topside apertures and bottomside apertures, while within an inner portion of the baffle plate for at least one of the topside surface and bottomside surface is a solid region throughout exclusive of any apertures. The inner portion has an outer dimension that is at least ten (10) percent of an outer dimension of the outer portion.

Abstract: A method of improving a plasma etch chamber by installing heaters on outer surfaces. A method of improving STI etch. A method of improving STI etch in a Hitachi M700 series etcher.