Patents by Inventor John Claassen Roberts

John Claassen Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170069744
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Applicant: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, James W. Cook, JR.
  • Publication number: 20170069484
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Applicant: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, James W. Cook, JR.
  • Patent number: 8343824
    Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 1, 2013
    Assignee: International Rectifier Corporation
    Inventors: Edwin Lanier Piner, Jerry Wayne Johnson, John Claassen Roberts
  • Patent number: 7569871
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: August 4, 2009
    Assignee: Nitronex Corporation
    Inventors: Walter H. Nagy, Jerry Wayne Johnson, Edwin Lanier Piner, Pradeep Rajagopal, John Claassen Roberts, Sameer Singhal, Robert Joseph Therrien, Andrei Vescan, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Kevin J. Linthicum
  • Publication number: 20080200013
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 21, 2008
    Applicant: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John Claassen Roberts, Pradeep Rajagopal
  • Patent number: 7352016
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: April 1, 2008
    Assignee: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Jerry Wayne Johnson, Kevin J. Linthicum, Edwin Lanier Piner, Pradeep Rajagopal, John Claassen Roberts, Sameer Singhal, Robert Joseph Therrien, Andrei Vescan
  • Patent number: 7352015
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: April 1, 2008
    Assignee: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John Claassen Roberts, Pradeep Rajagopal
  • Patent number: 7247889
    Abstract: III-nitride material structures including silicon substrates, as well as methods associated with the same, are described. Parasitic losses in the structures may be significantly reduced which is reflected in performance improvements. Devices (such as RF devices) formed of structures of the invention may have higher output power, power gain and efficiency, amongst other advantages.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 24, 2007
    Assignee: Nitronex Corporation
    Inventors: Allen W. Hanson, John Claassen Roberts, Edwin L. Piner, Pradeep Rajagopal
  • Patent number: 5851905
    Abstract: Stacked quantum well light emitting diodes include a plurality of stacked active layers of indium gallium nitride, separated by barrier layers of aluminum gallium nitride or aluminum indium gallium nitride, wherein the ratios of indium to gallium differ in at least two of the stacked active layers. Preferably, the differing ratios of indium to gallium are selected to produce emission wavelengths from the stacked active layers, such that the emission wavelengths are combined to produce white light. Controlled amounts of hydrogen gas are introduced into a reaction chamber during formation of indium gallium nitride or aluminum indium gallium nitride to produce high quality indium gallium nitride or aluminum indium gallium nitride which incorporate large percentages of indium and possesses excellent optical and surface properties.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: December 22, 1998
    Assignee: North Carolina State University
    Inventors: Forrest Gregg McIntosh, Salah Mohamed Bedair, Nadia Ahmed El-Masry, John Claassen Roberts
  • Patent number: 5684309
    Abstract: Stacked quantum well light emitting diodes include a plurality of stacked active layers of indium gallium nitride, separated by barrier layers of aluminum gallium nitride or aluminum indium gallium nitride, wherein the ratios of indium to gallium differ in at least two of the stacked active layers. Preferably, the differing ratios of indium to gallium are selected to produce emission wavelengths from the stacked active layers, such that the emission wavelengths are combined to produce white light. Controlled amounts of hydrogen gas are introduced into a reaction chamber during formation of indium gallium nitride or aluminum indium gallium nitride to produce high quality indium gallium nitride or aluminum indium gallium nitride which incorporate large percentages of indium and possesses excellent optical and surface properties.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: November 4, 1997
    Assignee: North Carolina State University
    Inventors: Forrest Gregg McIntosh, Salah Mohamed Bedair, Nadia Ahmed El-Masry, John Claassen Roberts