Abstract: A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Abstract: A hole saw for cutting standardized holes in the web portion of an I-joist features a light weight three spoke body having a rim with continuous circumference and three inserted cutting blades fixed in an offset to the circumference, which is dimensioned in accordance to standard web heights.

Abstract: A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Abstract: A support device is provided for the preferred application of buckling opposing support of an I-joist having an erroneously cut hole in its web portion. The support device may have an approximate U-shape with two substantially parallel bridging structures combined by a structure that combines the bridging structures and provides an alignment reference with the chords. In the case where an erroneously cut hole is identified, the support device may be laterally attached to the I-joist such that both bridging structures flank the erroneously cut hole. Once the bridging structures are attached to the web, the bridging structures define with the remainder of the web a buckling opposing interface. The support structure is preferably monolithically fabricated from sheet metal and scaled in conjunction with dimensional standards of commercially available I-joists.

Abstract: ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

Abstract: An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array.

Abstract: The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in thermal contact with the chalcogenide material. The semiconductor device may be used as memory element or as a programmable fuse.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: A method for designing load cells of articles, such as for example vehicle components. A computer model utilizes vehicle components as flexible members that are built and loaded mathematically such that the output can be used to determine the best location to lay the strain gages on the article based upon their corresponding Wheatstone bridge output. A suitable Finite Element Model (FEM) of the component to be instrumented is provided. This model is then loaded with the same loads the component will see in practice. Each load is independently applied to the model and the results from each load are saved. The Finite Element Analysis results needed by the present invention are the maximum and minimum principal strains and principal strain angle for each valid finite element in the model. These results along with the strain gage properties and some user preferences provide input data for assessing every usable combination of elements in the FEM for sensitivity to primary loads and cross-talk of off-axis loads.

Abstract: The process for converting feed materials of high mineral content containing primary metal values and fluorine values to the primary metal or useful compounds thereof and to fluorine values or useful compounds thereof, wherein the feed materials constitutes a difficultly soluble matrix, the process having the steps of contacting the feed materials in a reactor with a humidified, gaseous system at from about 200.degree. C. to about 1600.degree. C., the contacting being carried out such as to convert the primary metal values to oxide residues at commercially acceptable rates and to evolve gaseous fluoride from the feed, digesting said oxide residues in an acidic digest medium and separating the primary metal values from the resulting digest liquor and from other components of the residues.

Abstract: A capsule for oral administration of a pharmaceutically active ingredient contains a pharmaceutical composition comprising the active ingredient, for example, a peptide, an absorption promoter and usually, a carrier. The absorption promoter is capable of enhancing absorption of the active ingredient from the intestine into the bloodstream. The capsule is coated with a film forming composition, which film is sufficiently insoluble at a pH below 7 as to be capable of protecting the capsule and its contents from the digestive juices until the capsule reaches a region below the upper part of the intestine, whereupon the coating and capsule are capable of eroding or dissolving to release the active ingredient for absorption into the bloodstream.

Abstract: A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Abstract: An oscillator with noise rejection which may be used in a gate array in a semiconductor chip including a first amplifier circuit, a circuit, for connecting an external feedback element (crystal) across the input and inverting output of the first amplifier circuit for generating and amplifying a sine wave, and a circuit connected to the inverting output of the first amplifier circuit for generating a square wave with the duty cycle thereof being proportional to the difference between the center of the voltage swing of the amplified sine wave and a reference voltage. In a preferred embodiment, the first amplifier circuit and the generating circuit each include a current switch. A voltage reference network is provided to set the reference voltage for the current switch in the generating circuit to the center of the voltage swing of the sine wave applied to that current switch. This results in a 50% duty cycle square wave for the output signal.

Abstract: An oscillator with noise rejection and a fifty percent duty cycle for the on-chip generation and conversion of a sine wave to a square wave, using an external reference crystal. The circuit comprises a low gain current switch including a first and second switching transistors, with the control lines of the switching transistors connected to a reference voltage line. The reference crystal is connected across the control input and the current receiving terminals of the first transistor so that a square wave is obtained at the current receiving terminal of the second transistor. A threshold circuit is included for adjusting the voltage of the square wave signal from the second transistor and applying the adjusted signal to a diode-coupled receiver circuit, which provides the output for the circuit.

Abstract: An improved flue cleaner is provided having a scraper and an adjustable fulcrum assembly mounted on opposite sides of the end portion of an elongated rod. The fulcrum assembly includes a roller rotatably mounted on one end of a pivotable beam and is fixed in place by a bracket which is connected to the beam and to the rod in an adjustable fashion.

Abstract: The disclosure relates to apparatus for installing a clamp portion of an electrical connector to a multiconductor communication cable. The apparatus is used in conjunction with apparatus for trimming, and connecting, wires to electrical terminals of the connector.

Abstract: Apparatus is disclosed which includes a carriage having mounted thereon tooling for trimming wires and inserting trimmed wires into electrical contacts successively along an electrical connector mounted on an anvil. A stepping motor drive transports and repeatedly stops the carriage and the tooling successively in alignment with the multiple contacts preparatory to insertion of corresponding trimmed wires therein. The tooling is quickly replaceable and follows along a reference surface of the connector for positive alignment with the contacts.