Abstract: Power consumption of computing devices are monitored with performance counters and used to generate a power model for each computing device. The power models are used to estimate the power consumption of each computing device based on the performance counters. Each computing device is assigned a power cap, and a software-based power control at each computing device monitors the performance counters, estimates the power consumption using the performance counters and the model, and compares the estimated power consumption with the power cap. Depending on whether the estimated power consumption violates the power cap, the power control may transition the computing device to a lower power state to prevent a violation of the power cap or a higher power state if the computing device is below the power cap.

Abstract: A jackscrew nut and/or bolt head assembly includes a circumferentially and radially interlocked bottom washer. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary torque exerted onto the main body of the nut and/or bolt head via an outside spline such as well known triple square, twelve spline or the like, which may be incorporated also into the bottom washer for a concurrent application of an external torque. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced.

Abstract: A hardware device is used to accelerate query operators including Where, Select, SelectMany, Aggregate, Join, GroupBy and GroupByAggregate. A program that includes query operators is processed to create a query plan. A hardware template associated with the query operators in the query plan is used to configure the hardware device to implement each query operator. The hardware device can be configured to operate in one or more of a partition mode, hash table mode, filter and map mode, and aggregate mode according to the hardware template. During the various modes, configurable cores are used to implement aspects of the query operators including user-defined lambda functions. The memory structures in the hardware device are also configurable and used to implement aspects of the query operators. The hardware device can be implemented using a Field Programmable Gate Array or an Application Specific Integrated Circuit.

Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.

Abstract: A jackscrew nut and/or bolt head assembly includes a bottom washer that is interlocked via circumferentially arrayed castle extensions and recesses. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary pre tightening torque exerted onto the main body of the nut and/or bolt head via a tool that concurrently accesses all jackscrew heads extending above the main body. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced. The jackscrews are thinned in reverse for maximum contact area at their spherical bottoms.

Abstract: A jackscrew nut and/or bolt head assembly includes a load washer that may be selectively engaged via the jackscrews. Spherical faces at the washer top are held in alignment with corresponding spherical jackscrew bottoms via axially interlocking pins. The pins may partially extend radial beyond the circumference of the main body of the nut and/or bolt head thereby defining ridges of an outside tool access profile. The assembly may be initially tightened via a primary torque induced onto the pins and the main body. Final tightening and load setting may be provided via the jackscrews whereby a lock feature of the load washer may be engaged and the assembly secured against inadvertent loosening. The load washer may be part of a lock washer stack including a lock washer. The interface between the lock and load washer may be configured for ratchet locking and/or helical wedge locking of the central thread.

Abstract: A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Abstract: A universal single-bitstream FPGA library or ASIC implementation accelerates matrix-vector multiplication processing multiple matrix encodings including dense and multiple sparse formats. A hardware-optimized sparse matrix representation referred to herein as the Compressed Variable-Length Bit Vector (CVBV) format is used to take advantage of the capabilities of FPGAs and reduce storage and bandwidth requirements across the matrices compared to that typically achieved when using the Compressed Sparse Row (CSR) format in typical CPU- and GPU-based approaches. Also disclosed is a class of sparse matrix formats that are better suited for FPGA implementations than existing formats reducing storage and bandwidth requirements. A partitioned CVBV format is described to enable parallel decoding.

Abstract: A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.

Abstract: Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.

Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

Abstract: A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Abstract: A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

Abstract: Power consumption of computing devices are monitored with performance counters and used to generate a power model for each computing device. The power models are used to estimate the power consumption of each computing device based on the performance counters. Each computing device is assigned a power cap, and a software-based power control at each computing device monitors the performance counters, estimates the power consumption using the performance counters and the model, and compares the estimated power consumption with the power cap. Depending on whether the estimated power consumption violates the power cap, the power control may transition the computing device to a lower power state to prevent a violation of the power cap or a higher power state if the computing device is below the power cap.

Abstract: Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.

Abstract: A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.

Abstract: A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.

Abstract: An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.

Abstract: A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.