Abstract: An actuation and reaction socket tool features a reaction coupling that is slid onto the spline flange of a power torque wrench prior to attaching the actuation socket on the drive shaft of the torque wrench and prior to securing it with a well-known safety pin. The reaction coupling is then coupled to the reaction socket via circumferentially arrayed and interlocking castles on both the reaction coupling and reaction socket. A lock plate spring loaded snaps into grooves on the inside of the castles and axially locks the reaction coupling with the reaction socket. At least one of the reaction coupling and reaction socket is axially withheld by the central actuation socket such that the entire tool system remains connected to the torque wrench. To remove the tool again, the reaction coupling and reaction socket are first decoupled, which provides access again to the safety pin for its removal.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Abstract: Interchangeable monolithic or stacked Belleville reaction washers initially penetrate with outward bottom serration edges only during manual pre-tightening. Slippage is thereby avoided at begin of the consecutive power torque wrench assisted full tightening of the nut and/or bolt head resting on it. As the load ramps up, the reaction washer or stack flattens out and the bottom serrations gradually penetrate radially inwards. Reaction and actuation sockets of varying sizes matching a broad range of reaction washers and nut and/or bolt heads may be interchangeably snapped on a reaction coupling connected to the torque wrench housing. A clearance undercut underneath the reaction washer torque receiving flanges captures eventual debris to further assist unimpeded and fast coupling of the system. Radially oriented contact faces between reaction washer and reaction socket provide a snug contact unaffected by their toroidal movement during washer flattening and a force transfer free of radial force components.

Abstract: A Belleville reaction washer flattens out while being fully loaded such that its bottom serrations initially contact and bite with their peripheral ends only. Thereby washer slippage is circumvented as the maximum distance to the washer axis offsets eventual increased thread friction and eventual presence of lubricants or paint on the base surface. During washer flattening, the bottom serrations extend their bite radially inward and underneath the nut or bolt head. The Belleville spring action may secure the nut or bolt head on top against inadvertent loosening. In addition, a dual washer stack may include a conical ramp interface for a low overall height and lock washer functionality. Radial torque receive faces remain in plane during washer flattening and receive the torque substantially free of radial force components. A radially slim reaction socket interface may thus be tapered down around them without need for continuous circumferential structural support.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: Accurate reaction socket access within an outer washer diameter is provided via a number of tool access castles extending from a stepped bushing and serration top, which in turn provides low friction during initial tightening and securing after final loading of a nut/bolt. Bottom serration slipping during initial tightening and thread locking during initial loosening are eliminated by the reaction washer stacked on top and in contact with a support washer via helical ramps and ramp mates. During initial tightening or loosening, the ramp mates slide up or down the helical ramps whereby an axial load on the nut/bolt is ramped up or down prior to screwing it on the main thread. A clamp ring or ramp indenters may secure the two washers. An interposition washer may extend the axial reaction range of the washer stack. Direct tension indicators may be combined with the ramp indenters.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: An actuation and reaction socket tool features a reaction coupling that is slid onto the spline flange of a power torque wrench prior to attaching the actuation socket on the drive shaft of the torque wrench and prior to securing it with a well known safety pin. The reaction coupling is then coupled to the reaction socket via circumferentially arrayed and interlocking castles on both the reaction coupling and reaction socket. A lock plate spring loaded snaps into grooves on the inside of the castles and axially locks the reaction coupling with the reaction socket. At least one of the reaction coupling and reaction socket is axially withheld by the central actuation socket such that the entire tool system remains connected to the torque wrench. To remove the tool again, the reaction coupling and reaction socket are first decoupled, which provides access again to the safety pin for its removal.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: Accurate reaction socket access within an outer washer diameter is provided via a number of tool access castles extending from a stepped bushing and serration top, which in turn provides low friction during initial tightening and securing after final loading of a nut/bolt. Bottom serration slipping during initial tightening and thread locking during initial loosening are eliminated by the reaction washer stacked on top and in contact with a support washer via helical ramps and ramp mates. During initial tightening or loosening, the ramp mates slide up or down the helical ramps whereby an axial load on the nut/bolt is ramped up or down prior to screwing it on the main thread. A clamp ring or ramp indenters may secure the two washers. An interposition washer may extend the axial reaction range of the washer stack. Direct tension indicators may be combined with the ramp indenters.

Abstract: A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval.

Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.