Patents by Inventor John D. Hopkins

John D. Hopkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081052
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins
  • Publication number: 20240081070
    Abstract: Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Alyssa N. Scarbrough, John D. Hopkins, Jordan D. Greenlee
  • Publication number: 20240081057
    Abstract: An electronic device includes a source contact adjacent to a source stack, the source stack including one or more conductive materials, tiers of alternating conductive material and dielectric materials adjacent to the source contact, pillars extending vertically through the tiers and the source contact and at least partially into the source contact, a fill material extending vertically through the tiers to the source contact, and a metal silicide material between the fill material and an upper surface of the source contact. Related devices, systems, and methods are also disclosed.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Andrew L. Li
  • Patent number: 11922950
    Abstract: A method according to one embodiment includes receiving audio input by a microphone of an access control device that controls access through a passageway, processing an audio signal associated with the audio input to identify and authenticate a user, determining a command corresponding with the audio signal in response to identification and authentication of the user, and performing at least one action that corresponds with the command.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 5, 2024
    Assignee: Schlage Lock Company LLC
    Inventors: Daniel Langenberg, Joseph W. Baumgarte, Joshua Long, Brady Plummer, John D. Goodwin, Dakoda Johnson, Benjamin J. Hopkins, Robert Prostko, Robert Martens
  • Patent number: 11923415
    Abstract: Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: March 5, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins
  • Patent number: 11925016
    Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Publication number: 20240071496
    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20240074178
    Abstract: An electronic device comprising one or more blocking regions. The electronic device also comprises a source stack comprising one or more conductive materials, a source contact vertically adjacent to the source stack, and a doped semiconductive material vertically adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are vertically adjacent to the doped semiconductive material, and pillars extend through the tiers of alternating conductive materials and dielectric materials, the doped semiconductive material, and the source contact and into the source stack. The one or more blocking regions are laterally adjacent to the semiconductive material. Additional electronic devices, electronic systems, and methods are also disclosed.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventor: John D. Hopkins
  • Publication number: 20240070763
    Abstract: Methods, apparatus, and non-transitory machine-readable media associated with sale of virtual goods based on physical location are described. An apparatus can include a memory device and a processing device communicatively coupled to the memory device. The processing device can detect a computing device within a threshold radius of a first physical location, display a virtual environment associated with the physical location via a user interface of the computing device, and provide a virtual good for sale via the user interface based on a second physical location of the computing device within the first physical location.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: John D. Hopkins, Mohad Baboli
  • Publication number: 20240074183
    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise a first flight of the treads and a second flight of the treads. A landing is between and lower in the stack than each of the first and second flights of treads.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20240074202
    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. An anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. The anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. Individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. Other aspects, including structure independent of method, are disclosed.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20240074179
    Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc
    Inventors: John D. Hopkins, Damir Fazil, Jordan D. Greenlee
  • Publication number: 20240074182
    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. Methods are also disclosed.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Patent number: 11915974
    Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Shuangqiang Luo, Alyssa N. Scarbrough
  • Patent number: 11917817
    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, John D. Hopkins, Lifang Xu, Nancy M. Lomeli, Indra V. Chary, Kar Wui Thong, Shicong Wang
  • Patent number: 11916024
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11910601
    Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, John D. Hopkins, Matthew J. King, Roger W. Lindsay, Kevin Y. Titus
  • Patent number: 11910596
    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Alyssa N. Scarbrough, John D. Hopkins
  • Patent number: 11910606
    Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Publication number: 20240057335
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 15, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins