Abstract: A method of identifying a full range of patentable aspects of an invention, the invention including broad and narrow aspects and includes the following steps. First, defining a first aspect of the invention, defining a first invention type of the invention, and defining a life cycle aspect of the invention. Second, modifying the first aspect while holding constant the first invention type and the life cycle aspect. Third, repeating the first and second steps until all the patentable aspect of the invention is defined.

Abstract: A method and system for recording and tracking the progress of a plurality of inventions through an Invention Method including IP Mapping, IP Strategy, IP Generation, IP Documentation, IP Review Board, and IP Patenting or Provisional Filing, utilizing a Database platform comprising a plurality of tables, view screens, and reports that characterize the flow of an invention from one method through to the next, from the time an invention is identified until it is patented, and even beyond issuance, or until some other disposition of the invention is made.

Abstract: In general, in one aspect, the invention features a method of facilitating the conception of one or more inventions in a target market and/or technology areas by a group of one or more participants. The method may include the following; a set of one or more steps accomplished by a facilitator, and may include one or more of the following steps. First, communicating guidelines for creative thinking to the participants, wherein the guidelines for creative thinking may include creativity tools.

Abstract: A method for providing information to a least one potential customer from an individual business owner the individual business owner belonging to a group of many business owners, which includes the following steps. First, setting up a web-site on a server, the web-site being accessed via a network by using a group uniform resource locator (URL) address, and comprising business information being common to the group of many business owners, and customized information being customized to the individual business owner. Second, supplying collateral material to the at least one potential customer, the collateral material comprising the group URL referring to the web-site, and a first unique site-code. Third, accessing the web-site by the at least one potential customer using the group URL. Fourth, inputting the first unique site-code to an input field of the web-site by the at least one potential customer.

Abstract: The present invention provides an apparatus and methods for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: An apparatus and method are provided that remove sufficient heat from both SOI and non-SOI semiconductor devices to prevent the devices from overheating during operation. A plurality of thermally conductive pads such as electrically conductive studs are coupled to a first side of a semiconductor device having circuit elements formed thereon. The thermally conductive pads also are coupled to a substrate comprising an apparatus for extracting heat from the thermally conductive pads. The apparatus for extracting heat from the thermally conductive pads preferably comprises one or more metallic planes. A module cover having a thermally conductive path formed therein also may be coupled between the apparatus for extracting heat and a heat sink to further aid in heat removal from the semiconductor device. Thermally conductive pads may be coupled between the semiconductor device and I/O pins of the substrate to improve heat dissipation via the I/O pins.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: An apparatus used for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.

Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.

Abstract: A method for temporarily attaching an electrical component to a pad, testing the component, removing and replacing the component if necessary, and making a final attachment of the component to the pad. The method provides for attachment and removal of components, to and from pads located on the substrate of a printed circuit board, wherein the method enables components to be easily removed prior to final assembly without damaging the circuit board or components mounted thereon. The method utilizes a layer of conductive, radiation-curable adhesive placed between the component's lead and the pad. Radiation is then directed through a mask onto a portion of the adhesive layer, which cures the portion while leaving a remaining area of the adhesive layer uncured. Because the portion of the adhesive layer that receives the radiation, and is consequently cured by the radiation, is only a limited portion of the whole adhesive layer, the component may be easily removed from the pad by applying a small mechanical force.

Abstract: A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer.

Abstract: A method for forming a semiconductor trench capacitor cell having a buried strap uses a substrate having a trench with a conductor separated from walls of the trench by a dielectric material. A portion of the dielectric material to a level below a top surface of the conductor is removed and at least a portion of the space thus formed is filled with a diffusible material. The buried strap is formed by annealing the conductor, the wall and the diffusible material so that conductive elements from the wall and the conductor diffuse into the diffusible material.

Abstract: A semiconductor device which includes a first semiconductor chip mounted on top of a lead frame which is molded within a plastic body. During the molding process a cavity is formed on the bottom of the lead frame. After testing or burn-in of the first chip a second semiconductor chip is mounted and electrically connected to the lead frame. The second chip may then be sealed within the cavity to form a multichip module.

Abstract: The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

Abstract: A polishing pad and method of polishing with a chemical mechanical planarization apparatus includes providing a bulk polishing pad material having a front polishing surface side and a back side. The polishing pad further includes a polishing pad wear indicator for indicating a polishing pad wear during a life cycle of the polishing pad. The polishing pad wear indicator is formed on the back side of the bulk polishing pad material.

Abstract: Microconnectors are described that can be fabricated on circuitry, the microconnectors for physically and/or electrically connecting separate structures. The microconnectors permit partitioning of a function among a plurality of chips. The microconnectors include a latching member.

Abstract: Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.

Abstract: The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

Abstract: A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.