Abstract: An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.

Abstract: An integrated circuit capacitor device that increases capacitance without proportionately using more substrate surface area. Uniquely, the capacitor uses up to all four sides of the first charge plate to store charge by surrounding it with a second charge plate with an insulator layer separating the two plates.

Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact.

Abstract: A chemical mechanical planarization tool and method are presented employing a non-linear motion of the carrier arm relative to the polishing pad. The non-linear motion of the carrier arm relative to the polishing pad can be accomplished in a variety of ways, for example, employing a mechanical template having an irregular opening or programming the carrier displacement mechanism to move the carrier in an irregular, non-rotational X-Y path over the polishing pad.

Abstract: Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

Abstract: A chimney capacitor is formed having two plates, of which each is disposed above and contacts a corresponding electrical contact. The electrical contacts facilitate electrical access to the plates of the chimney capacitor. One of the electrical contacts may comprise part of a general wiring layer that may be used for both electrically accessing the capacitor and for general wiring within the IC chip. Formation of the chimney capacitor proceeds by first forming two electrical contacts on an integrated circuit ("IC") chip. A planar insulating layer is formed thereover, and the capacitor is formed at least partially within the planar insulating layer such that each plate is electrically connected to a corresponding electrical contact.

Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.

Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.

Abstract: Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.

Abstract: A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.

Abstract: Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

Abstract: A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers.

Abstract: A micro electrostatic cooling fan arrangement is provided which includes a heat source having a planar surface, a stator attached to the heat source, an axle attached to the heat source and spaced from the stator, a rotary element including a hub having an aperture therein and a fan blade, the axle passing through the aperture of the hub and the fan blade having a major surface thereof disposed at an angle with respect to the surface of the heat source and attached to the hub at one end, with the other end of the fan blade being adjacent to but spaced from the stator and a voltage source applied to the stator having sufficient voltage to charge the fan blade.