Abstract: A method is disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

Abstract: A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses). A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip.

Abstract: A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip.

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract: An apparatus and method are disclosed for measuring bias of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias of the polysilicon shapes relative to the silicon area.

Abstract: An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.

Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

Abstract: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

Abstract: An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.

Abstract: An apparatus for measuring alignment of polysilicon shapes to a silicon area. Each polysilicon shape in a first plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. Each polysilicon shape in a second plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. The second plurality of silicon shapes is positioned on the opposite side of the silicon area from the first plurality of silicon shapes. An electrical measurement of how many of the polysilicon shapes in the first plurality of polysilicon shapes and in the second plurality of polysilicon shapes provides a measurement of alignment of the polysilicon shapes and the silicon area.

Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.

Abstract: Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress condition. Many storage elements in an electronic system store the same data for virtually the life of the system, resulting in significant BTI caused VT shifts in FETs in the storage elements. An embodiment of the invention ensures that a particular storage element is in a first state for a first portion of time the electronic system operates, during which data is stored in a storage element in a first phase, and that the particular storage element is in a second state for a second portion of time the electronic system operates, during which data is stored in the storage element in a second phase.

Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.

Abstract: Circuitry and methods are disclosed for quantitatively characterizing the delay of Embedded Dynamic Random Access Memory (EDRAM) and Dynamic Random Access Memory (DRAM). The performance critical portion of the memory is placed in a ring oscillator designed such that the delay through the portion, from a rising input to the memory to a rising output, can be accurately determined. Recently, such memory elements have begun to be implemented on chips along with high-speed logic circuitry. However, the performance characteristics of the memory elements do not track the performance characteristics of the logic circuitry. The current invention allows the memory performance to be characterized along with, or separately from, characterization of the logic circuitry.

Abstract: Circuitry and methods are disclosed for quantitatively characterizing the delay of Embedded Dynamic Random Access Memory (EDRAM) and Dynamic Random Access Memory (DRAM). The performance critical portion of the memory is placed in a ring oscillator designed such that the delay through the portion, from a rising input to the memory to a rising output, can be accurately determined. Recently, such memory elements have begun to be implemented on chips along with high-speed logic circuitry. However, the performance characteristics of the memory elements do not track the performance characteristics of the logic circuitry. The current invention allows the memory performance to be characterized along with, or separately from, characterization of the logic circuitry.

Abstract: Silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening.

Abstract: A method and apparatus for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS). A capacitor is operatively coupled between the base and emitter terminals of the parasitic bipolar transistor. The capacitor effectively reduces the base to emitter voltage of the parasitic transistor thereby reducing leakage current generated at the collector terminal.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.