Abstract: Methods and silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: An SRAM memory cell made with increased stability using SOI technology is provided. Increased stability occurs because of raising the threshold voltage of the transfer nfets connected to the word line. Preferably the increase of threshold voltage is achieved using boron ion implantation.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.

Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.

Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.

Abstract: The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor comprises a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: A semiconductor-on-insulator integrated circuit with buried patterned layers as electrical conductors for discrete device functions, thermal conductors, and/or decoupling capacitors.

Abstract: A driver circuit for providing reduced AC defects includes an output driver transistor with an effective compensation resistor coupled to a control input of the output driver transistor. An input signal is coupled to the control input of the output driver transistor through the compensation resistor. A current sensing detector is coupled between the compensation resistor and the control input of the output driver transistor for detecting an AC defect responsive to an applied input signal. A field effect transistor can be used for the current sensing detector. Also a differential amplifier can be used for the current sensing detector for detecting smaller AC defects.

Abstract: The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor includes a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.