Patents by Inventor John F. Kaeding
John F. Kaeding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908814Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.Type: GrantFiled: May 24, 2021Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: John F. Kaeding, Owen R. Fay
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Publication number: 20230397390Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: August 15, 2022Publication date: December 7, 2023Inventors: David K. Hwang, John F. Kaeding, Matthew S. Thorum, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, Yoshitaka Nakamura, Glen H. Walters
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Publication number: 20230397392Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: August 15, 2022Publication date: December 7, 2023Inventors: John F. Kaeding, Matthew S. S. Thorum
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Patent number: 11728276Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.Type: GrantFiled: August 30, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventor: John F. Kaeding
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Publication number: 20230198139Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.Type: ApplicationFiled: February 16, 2023Publication date: June 22, 2023Inventors: John F. Kaeding, Owen R. Fay
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Patent number: 11670707Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: June 14, 2022Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
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Patent number: 11588233Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.Type: GrantFiled: July 25, 2018Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: John F. Kaeding, Owen R. Fay
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Publication number: 20220310831Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: June 14, 2022Publication date: September 29, 2022Applicant: Micron Technology, Inc.Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
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Patent number: 11393920Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: September 28, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
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Publication number: 20220102539Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Applicant: Micron Technology, Inc.Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
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Publication number: 20220102384Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.Type: ApplicationFiled: September 2, 2021Publication date: March 31, 2022Inventors: Glen H. Walters, John A. Smythe III, Scott E. Sills, John F. Kaeding
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Publication number: 20220028820Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.Type: ApplicationFiled: September 30, 2021Publication date: January 27, 2022Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
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Patent number: 11227777Abstract: A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.Type: GrantFiled: October 9, 2018Date of Patent: January 18, 2022Assignee: Micron Technology, Inc.Inventor: John F. Kaeding
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Publication number: 20210391267Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventor: John F. Kaeding
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Patent number: 11139262Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.Type: GrantFiled: February 7, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
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Publication number: 20210280538Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: John F. Kaeding, Owen R. Fay
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Patent number: 11114383Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.Type: GrantFiled: October 23, 2018Date of Patent: September 7, 2021Assignee: Micron Technology, Inc.Inventor: John F. Kaeding
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Patent number: 11018098Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.Type: GrantFiled: August 31, 2018Date of Patent: May 25, 2021Assignee: Micron Technology, Inc.Inventors: John F. Kaeding, Owen R. Fay
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Publication number: 20200258859Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.Type: ApplicationFiled: February 7, 2019Publication date: August 13, 2020Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
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Publication number: 20200126917Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.Type: ApplicationFiled: October 23, 2018Publication date: April 23, 2020Inventor: John F. Kaeding