Patents by Inventor John F. Kaeding

John F. Kaeding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310831
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Patent number: 11393920
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220102384
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 31, 2022
    Inventors: Glen H. Walters, John A. Smythe III, Scott E. Sills, John F. Kaeding
  • Publication number: 20220102539
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220028820
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 27, 2022
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Patent number: 11227777
    Abstract: A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John F. Kaeding
  • Publication number: 20210391267
    Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventor: John F. Kaeding
  • Patent number: 11139262
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20210280538
    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: John F. Kaeding, Owen R. Fay
  • Patent number: 11114383
    Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: John F. Kaeding
  • Patent number: 11018098
    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John F. Kaeding, Owen R. Fay
  • Publication number: 20200258859
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20200126917
    Abstract: Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Inventor: John F. Kaeding
  • Publication number: 20200111683
    Abstract: A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventor: John F. Kaeding
  • Patent number: 10593568
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10586780
    Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Publication number: 20200075512
    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: John F. Kaeding, Owen R. Fay
  • Patent number: 10566686
    Abstract: A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 18, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: John F. Kaeding, Owen R. Fay
  • Publication number: 20200036093
    Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: John F. Kaeding, Owen R. Fay
  • Publication number: 20200006845
    Abstract: A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: John F. Kaeding, Owen R. Fay