Abstract: According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

Abstract: Methods, apparatus and machine-readable medium are described to terminate a memory bus line. In some embodiments, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memory bus line during a memory write.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bidirectional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: A method and apparatus for control calibration of multiple memory modules within a memory channel is described. The method selects a memory channel from one or more memory channels coupled to a controller. Next, a memory module, coupled to the memory channel, is selected. A path delay is then determined for the selected memory module. The path delay includes a time interval for receipt of a data signal following issuance of a command by the controller to the selected memory module. Once determined, the path delay is stored, such that when the controller issues a command to a selected memory module, a controller receiver is enabled to capture a data signal following a time interval, as defined by the path delay, from issuance of the command. This process is repeated until a path delay is determined for each memory module of each memory channel coupled to the controller.

Abstract: According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: A DDR apparatus is provided that includes a pattern generating device to generate a clock test pattern and a data test pattern and buffer devices to receive the clock test pattern and the data test pattern. A pattern checking device checks patterns received from the buffer devices. Clock generating logic controls a clock for the clock test pattern and a clock for the data test pattern.

Abstract: A system and method in which delay strobe variation in a double data rate device is calibrated by first individually calibrating all slave strobe delay devices at system startup. Thereafter, a master strobe delay device is activated periodically to determine an incremental delay adjustment. This incremental delay adjustment is then used to by the slave strobe delay devices to modify the calibration value performed by the slave strobe delay devices upon startup. In this manner, individual on-die variations are compensated for each slave strobe delay device and variations due to voltage and temperature changes are compensated for without effecting the normal operation of the slave strobe devices.

Abstract: A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.

Abstract: A system and method in which delay strobe variation in a double data rate device is calibrated by first individually calibrating all slave strobe delay devices at system startup. Thereafter, a master strobe delay device is activated periodically to determine an incremental delay adjustment. This incremental delay adjustment is then used to by the slave strobe delay devices to modify the calibration value performed by the slave strobe delay devices upon startup. In this manner, individual on-die variations are compensated for each slave strobe delay device and variations due to voltage and temperature changes are compensated for without effecting the normal operation of the slave strobe devices.

Abstract: A method and apparatus for control calibration of multiple memory modules within a memory channel is described. The method selects a memory channel from one or more memory channels coupled to a controller. Next, a memory module, coupled to the memory channel, is selected. A path delay is then determined for the selected memory module. The path delay includes a time interval for receipt of a data signal following issuance of a command by the controller to the selected memory module. Once determined, the path delay is stored, such that when the controller issues a command to a selected memory module, a controller receiver is enabled to capture a data signal following a time interval, as defined by the path delay, from issuance of the command. This process is repeated until a path delay is determined for each memory module of each memory channel coupled to the controller.

Abstract: A method for reading data from a memory device, according to an embodiment of the invention, is disclosed. A strobe signal from the memory device is not forwarded by a controller until after a predetermined time interval following the sending of a read command by the controller to the memory device. A first bit value is captured, according to the forwarded strobe signal, in a data signal also from the memory device. The predetermined time interval is at least as long as a roundtrip flight time interval of a reference pulse that is transmitted from the controller to the memory device and back to the controller.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: A method for reading data from a memory device, according to an embodiment of the invention, is disclosed. A strobe signal from the memory device is not forwarded by a controller until after a predetermined time interval following the sending of a read command by the controller to the memory device. A first bit value is captured, according to the forwarded strobe signal, in a data signal also from the memory device. The predetermined time interval is at least as long as a roundtrip flight time interval of a reference pulse that is transmitted from the controller to the memory device and back to the controller.

Abstract: According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

Abstract: In one embodiment of the invention, a delay circuit generates a plurality of delay strobe signals from a plurality of data strobe signals during an operational mode and a calibration signal from a reference signal by an interval during a calibration mode. The plurality of delay strobe signals clocks a plurality of data into a plurality of registers. A calibrator adjusts the interval according to a timing relationship between the calibration signal and the reference signal.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A fault-tolerant data processing system includes first and second microcircuits in a master/checker configuration. The first and second microcircuits perform identical transforming operations on identical data to generate respective outputs. The internal state of each microcircuit is encoded to a short code word and communicated to an external comparator. The comparator compares the encoded internal state data of the first and second microcircuits to determine if an error has occurred. Low error detection latency may be realized due to increased frequency of error detection, with minimal hardware and performance overhead.

Abstract: An instruction flow monitoring mechanism performs control flow error detection in a reduced instruction set computer (RISC) processor using signature monitoring. The signature monitoring is integrated into the RISC processor such that the instruction set of the RISC processor is enhanced to perform signature checking under all execution conditions. A signature monitor instruction causes the instruction flow to be checked for errors by comparing a pre-computed reference signature with a current signature and raising an error condition if the two signatures are unequal. The instruction also initializes the current signature.