Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: An aqueous solution of a cerium (IV) complex or salt having an extended lifetime is provided. In one embodiment, the extended lifetime is achieved by adding at least one booster additive to an aqueous solution of the cerium (IV) complex or salt. In another embodiment, the extended lifetime is achieved by providing an aqueous solution of a cerium (IV) complex or salt and a cerium (III) complex or salt. The cerium (III) complex or salt can be added or it can be generated in-situ by introducing a reducing agent into the aqueous solution of the cerium (IV) complex or salt. The aqueous solution can be used to remove a mask material, especially an ion implanted and patterned photoresist, from a surface of a semiconductor substrate.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

Abstract: The present disclosure relates to semiconductor device manufacturing and, more particularly, to removing a mask material, especially an ion implanted and patterned photo resist, using an aqueous cerium-containing solution. The present invention relates to a method and apparatus for cleaning the chemical materials utilized for cleaning semiconductor wafers. The invention utilizes a centrifugal filter to eliminate heavy materials from the cleaning solution.

Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.

Abstract: Embodiments of the present invention relate to detecting leaks in a fluid cooling system. One aspect of the present invention concerns an apparatus for detecting leaks in a fluid cooling system that includes a pressure exerting device for applying a pressure on a supply hose and a return hose of the cooling system, and a pressure gauge coupled to the pressure exerting device for detecting a drop of fluid pressure in the cooling system while the pressure is applied. The drop of fluid pressure indicates that there may be a leak in the cooling system.

Abstract: An aqueous solution of a cerium (IV) complex or salt having an extended lifetime is provided. In one embodiment, the extended lifetime is achieved by adding at least one booster additive to an aqueous solution of the cerium (IV) complex or salt. In another embodiment, the extended lifetime is achieved by providing an aqueous solution of a cerium (IV) complex or salt and a cerium (III) complex or salt. The cerium (III) complex or salt can be added or it can be generated in-situ by introducing a reducing agent into the aqueous solution of the cerium (IV) complex or salt. The aqueous solution can be used to remove a mask material, especially an ion implanted and patterned photoresist, from a surface of a semiconductor substrate.

Abstract: A method of identifying a substitute chemical includes receiving, at a computer, a trial set of properties that describes a function in a desired chemical process of a chemical for substitution, performing a distributed search using objective similarity criteria based on the trial set of properties to identify a first set of candidate chemicals, prioritizing the first set of candidate chemicals into a second set of candidate chemicals, determining Environmental, Health, and Safety (EHS) data parameter values for each chemical of the second set of candidate chemicals, normalizing disparate EHS data parameter values into associated EHS properties, prioritizing the second set of candidate chemicals into a third set of candidate chemicals, and prioritizing the third set of candidate chemicals into a fourth set of candidate chemicals according to the risk posed by the desired chemical process.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Abstract: A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.