Abstract: Systems and methods for detecting and correcting Hyper Frame Number (HFN) desynchronization between a first radio node and a second radio node are disclosed. In one embodiment, a first radio node receives a Packet Data Convergence Protocol (PDCP) Packet Data Unit (PDU) from a second radio node and deciphers the PDCP PDU based on a PDCP Sequence Number (SN) contained in the PDCP PDU and a HFN maintained at the first radio node. The first radio node detects a PDCP SN gap with respect to the PDCP SN contained in the PDCP PDU and, in response, determines whether a HFN desynchronization condition exists between the first radio node and the second radio node. In response to determining that a HFN desynchronization condition exists between the first radio node and the second radio node, the first radio node increments the HFN maintained at the first radio node.

Abstract: The present invention provides a method and apparatus for separating air from a fluid, such as syrup, as the fluid enters a first chamber of a system; passing the fluid from the first chamber to a second chamber via a first device; passing the air from the first chamber to the second chamber via a second device so as to reintroduce the air back into the fluid and form a new fluid mixture having more uniform air bubbles; and discharging the new fluid out of the system.

Abstract: The present invention provides a device for turning off a pump. In operation, when the device is activated there is vacuum pressure in a syrup chamber. A diaphragm acting in response to the vacuum causes a piston assembly in the syrup chamber to move in the one direction (e.g. right), thus compressing a W-shaped spring in the air chamber. As the piston assembly moves, a spring holder of the W-shaped spring also moves to the one direction. As the W-shaped spring is compressed over and passed the most compressed position, the W-shaped spring moves a valve assembly in the air chamber to an opposite direction (e.g. left) and blocks a hole in a spool that otherwise allows air to pass through the air chamber to activate the pump. When the air is stopped, this turns off the pump.

Abstract: A photocurable composition comprising cationically curable compound, an acrylate-containing compound; a hydroxyl-containing compound; a cationic photoinitiator; and a free radical photoinitiator; wherein said composition has less than 0.54 equivalents of cationically curable groups, less than 0.10 equivalents of acrylate groups and less than 0.10 equivalents of hydroxyl 0groups per 100 grams of said composition.

Abstract: The present invention provides a method and apparatus for separating air from a fluid, such as syrup, as the fluid enters a first chamber of a system; passing the fluid from the first chamber to a second chamber via a first device; passing the air from the first chamber to the second chamber via a second device so as to reintroduce the air back into the fluid and form a new fluid mixture having more uniform air bubbles; and discharging the new fluid out of the system.

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Abstract: A photocurable composition, including (a) a cationically curable monomer; (b) a radically curable monomer; (c) reactive particles comprising a crosslinked polysiloxane core and a shell of reactive groups on an outer surface of the core, wherein the reactive groups comprise epoxy groups, ethylenically unsaturated groups, or hydroxy groups; (d) a radical photoinitiator; and (e) a cationic photoinitiator. A method of making a 3-D object from such a composition. A 3-D object made by the method.

Abstract: A photocurable composition comprising cationically curable compound, an acrylate-containing compound; a hydroxyl-containing compound; a cationic photoinitiator; and a free radical photoinitiator; wherein said composition has less than 0.54 equivalents of cationically curable groups, less than 0.10 equivalents of acrylate groups and less than 0.10 equivalents of hydroxyl 0 groups per 100 grams of said composition.

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract: A pump providing fault protection based on a controller receiving sensed pressure values from a pressure sensor included in a cavity of the pump, so as to be integral with the pump.

Abstract: A photocurable composition comprising cationically curable compound, an acrylate-containing compound; a hydroxyl-containing compound; a cationic photoinitiator; and a free radical photoinitiator; wherein said composition has less than 0.54 equivalents of cationically curable groups, less than 0.10 equivalents of acrylate groups and less than 0.10 equivalents of hydroxyl groups per 100 grams of said composition.

Abstract: Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.

Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Abstract: The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a decoder that selects local repair location addresses from repair sets 610 according to a repair region address 604. Comparators 616 compare the selected local repair location addresses with a local repair address 606 to identify a match. Repair register banks 622 that comprise a plurality of repair registers are selected if an associated comparator 606 identifies a match. Then, a register within the associated register bank is selected according the repair region address 604 for read/write access. If a match is not identified, a memory location from a main memory 630 is selected for read/write access.

Abstract: The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a repair verification router that compares a memory address 604 for a read/write request to a list or series of repair locations 608. On identifying a matching repair location, a repair register 616 located within a repair register bank 615 is coupled to a data bus 626. Otherwise, a memory location within the main memory 630 and addressed by the memory address 604 is coupled to the data bus 626.

Abstract: The present invention facilitates scaling of memory devices and operation thereof by employing a set associative repair cache system to correct or repair identified faulty memory cells. A repair cache region router 602 compares a repair region portion of a memory address to repair cache regions to identify a matching repair cache region. Then, a local repair location router 603 compares a repair address portion of the memory address to a local repair location addresses particular to the matching repair cache region to identify a matching local repair address. If a matching local repair address is identified, a repair component 606 provides access to a repair data location according to the matching local repair address and the matching repair cache region. Otherwise, a main memory 604 provides access to a memory location according to the memory address. Other systems and methods are disclosed.

Abstract: Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.