Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

Abstract: A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Abstract: An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

Abstract: A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output circuit comprises an input transistor which comprises a gate terminal coupled to the output terminal of the voltage-mode filter circuit, and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current-mode output circuit.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a baseband filter that can be used in a current-mode end-to-end signal path. The current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. In one or more embodiments, a device used in the signal path can comprise a baseband filter that receives an input current and outputs an output current. The baseband filter can comprise a feedback loop component having an active circuit branch and a passive circuit branch coupled in a loop. A mirroring device can be coupled to the feedback loop component and can provide an output of the device. Selectively activating the mirroring device can vary gain, such as of the mirroring device.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a baseband filter that can be used in a current-mode end-to-end signal path. The current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. In one or more embodiments, a device used in the signal path can comprise a baseband filter that receives an input current and outputs an output current. The baseband filter can comprise a feedback loop component having an active circuit branch and a passive circuit branch coupled in a loop. A mirroring device can be coupled to the feedback loop component and can provide an output of the device. Selectively activating the mirroring device can vary gain, such as of the mirroring device.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a baseband filter that can be used in a current-mode end-to-end signal path. The current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. In one or more embodiments, a device used in the signal path can comprise a baseband filter that receives an input current and outputs an output current. The baseband filter can comprise a feedback loop component having an active circuit branch and a passive circuit branch coupled in a loop. A mirroring device can be coupled to the feedback loop component and can provide an output of the device. Selectively activating the mirroring device can vary gain, such as of the mirroring device.

Abstract: Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can facilitate a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and analog outputs of the DAC and the upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path between a baseband filter and an output stage comprising the upconverting mixer. The device and/or system can be a radio frequency DAC. The diode-connected transistor can be programmable to vary gain and/or can be directly connected to the output stage absent a turnaround current mirror connected therebetween.

Abstract: A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

Abstract: A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Abstract: A transmitter (TX)-side feedforward equalizer (FFE) includes one or more “roaming” filter taps which can be used to compensate reflections that occur at unpredictable and substantial time offsets from a main pulse. The roaming filter taps are realized in a hardware- and power-efficient manner by implementing a programmable delay serializer in which the phases of multi-rate clocks are switched to introduce binary weighted delays on the roaming tap. In this way a variable difference in latencies is introduced between the main and the roaming tap data paths. The TX-side FFE implementations provide a fully programmable roaming tap generator having a 1-Unit Interval (UI) resolution of delay setting integrated into the data serializer of the TX macro.

Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Abstract: A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

Abstract: Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.

Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.

Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.