Patents by Inventor John Francis Bulzacchelli

John Francis Bulzacchelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7792185
    Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Francis Bulzacchelli, Matthew J. Park
  • Patent number: 7733984
    Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, John Francis Bulzacchelli, Daniel Mark Dreps
  • Publication number: 20100054324
    Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 4, 2010
    Inventors: John Francis Bulzacchelli, Gautam Gangasani, Mounir Meghelli, Sergey V. Rylov, Michael A. Sorna, Steven J. Zier
  • Publication number: 20080187037
    Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.
    Type: Application
    Filed: February 7, 2007
    Publication date: August 7, 2008
    Inventors: John Francis Bulzacchelli, Matthew J. Park
  • Publication number: 20080107212
    Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, John Francis Bulzacchelli, Daniel Mark Dreps