Abstract: In one example described, a data sequence generator for use in spread spectrum communications includes one or more read-only memories (ROMs) which have first and second spreading sequences stored therein. The first spreading sequence is associated with a first mode of communication, whereas the second spreading sequence is associated with a second mode of communication. The one or more ROMs have inputs to receive counter values and outputs for serially providing, responsive to the counter values, sequence data from either the first spreading sequence or the second spreading sequence depending on which mode of communication is selected. The first and the second spreading sequences may be unique to, for example, IS-95 and IS-2000 standards, respectively.

Abstract: An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode.

Abstract: Methods and apparatus for use in generating data sequences for direct sequence spread spectrum (DSSS) communications are described. One exemplary method includes the steps of serially generating a pseudo random noise (PN) sequence by, for each count value i of a plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i)th position in the PN sequence. The exemplary method includes the further steps of serially generating a Gold code sequence by, for each count value i of the plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i+n)th position in the PN sequence, retrieving from memory a bit of the PN sequence corresponding to the (q*i)th position in the PN sequence, and adding the bit corresponding to the (i+n)th position with the bit corresponding to the (q*i)th position.

Abstract: A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base station system time. Accurate timing is made possible through a number of techniques including precise initial calibration using a rising edge/falling edge averaging system, determining the sleep clock and reference clock frequencies, and the determination of the frequency drift of the sleep clock that occurred during the previous sleep interval.

Abstract: A system and method for shifting the phase of a PN code sequence are provided, useful in communications networks where power can be conserved by powering-off the PN clock and PN generators during slotted mode sleep intervals. The system and method targets a family of time intervals, and stores phase shifting masks corresponding to these probable intervals. The PN code generated with the phase-shifting mask at power-up is sufficiently accurate to permit rapid resynchronization. Further, because the phase-shifting masks do not have to be calculated, processing time is minimized and the PN clock and generators can be powered-off for longer periods of time.

Abstract: A Direct Sequence Spread Spectrum (DSSS) receiver system (100) combines and orders the soft symbols from associated information channels. The system permits a QPSK channel to be demodulated as a pair of BPSK channels, and the soft symbols of the demodulated BPSK channels to be multiplexed into a single information channel. The receiver system (100) includes a plurality of demodulating fingers (102-106). Each demodulating finger accepts modulation parameters and a sample stream, while supplying soft symbols with indexing information so that information channels can be subsequently multiplexed into a single information channel. A method for ordering the soft symbols of associated information channels in a DSSS system is also provided.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).

Abstract: A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C filter, adjustable resistance and reactance assemblies are coupled in series. The resistance assembly has multiple parallel signal paths sharing a common input and output. Each signal path includes a prescribed electrical resistance and a digital switch to selectively enable and disable the resistance. Between the common input and output, the signal paths provide a collective resistance which varies depending upon which switches have been activated. The reactance assembly is similar to the resistance assembly, with capacitors or inductors instead of resistors. A digital controller selectively activates the switches to adjust the assemblies' respective resistance and reactance.

Abstract: A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the data; and for each of a plurality of changes of the data, providing a selected PN bit of the PN sequence at an output of the memory based on the data.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).

Abstract: A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is described. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further includes a specifically designed block normalization circuitry.

Abstract: A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.

Abstract: A dual-mode communications processor disposed to be incorporated within a dual-mode communications device is disclosed herein. The dual-mode communications processor comprises a dual-mode voiceband signal processor having an input port for receiving digitized data. Within the dual-mode voiceband signal processor, first and second signal processing operations are performed upon the digitized data received during operation in first and second modes, respectively. These separate signal processing operations may advantageously be performed using common circuit elements within the dual-mode voiceband signal processor. In an exemplary embodiment the first signal processing operation is performed in accordance with a predefined vocoding algorithm, while the second signal processing operation involves the filtering of the digitized data as prescribed by FM cellular telephone standards.

Abstract: A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.

Abstract: A method and system, for use in a communication system in which data is transmitted in data frames of a predetermined time duration, for the positioning of the data within the data frames for transmission. A computation circuit computes according to the deterministic code a pseudorandom position for the data within each data frame. A positioning circuit positions the data within each data frame in the computed position.

Abstract: A method and system, for use in a communication system in which data is transmitted in data frames of predetermined time duration, for the positioning of the data within the data frames for transmission. A computation circuit computes according to the deterministic code a pseudorandom position for the data within each data frame. A positioning circuit positions the data within each data frame in the computed position.

Abstract: A method and system, for use in a communication system in which data is transmitted in data frames of a predetermined time duration, for the positioning of the data within the data frames for transmission. A computation circuit computes according to the deterministic code a pseudorandom position for the data within each data frame. A positioning circuit positions the data within each data frame in the computed position.