Patents by Inventor John G. Rell
John G. Rell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9436434Abstract: Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.Type: GrantFiled: March 14, 2014Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James R. Cuffney, John G. Rell, Jr., Eric M. Schwarz, Patrick M. West, Jr.
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Publication number: 20160210150Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: ApplicationFiled: December 28, 2015Publication date: July 21, 2016Inventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, JR.
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Publication number: 20160210153Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: ApplicationFiled: January 19, 2015Publication date: July 21, 2016Inventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, JR.
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Publication number: 20160210182Abstract: An apparatus for comparing strings comprises a first and a second set of input registers, a matrix of comparator circuits wherein rows of the matrix correspond to the first set of input registers and columns of the matrix correspond to the second set of input registers, a set of row control registers wherein each register corresponds to a row of the matrix of the comparator circuits, the matrix of comparator circuits configured to compare data provided by the first set of registers with data provided by the second set of registers according to the row control registers, and an error detection circuit configured to compare results from four comparator circuits corresponding to two adjacent rows and two columns of the matrix of comparator circuits. A method that invokes the above mentioned apparatus is also disclosed herein, along with a computer program product corresponding to the method.Type: ApplicationFiled: December 29, 2015Publication date: July 21, 2016Inventors: James R. Cuffney, Timothy J. Koprowski, John G. Rell, JR., Patrick M. West, JR.
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Publication number: 20160211850Abstract: An apparatus for comparing strings comprises a first and a second set of input registers, a matrix of comparator circuits wherein rows of the matrix correspond to the first set of input registers and columns of the matrix correspond to the second set of input registers, a set of row control registers wherein each register corresponds to a row of the matrix of the comparator circuits, the matrix of comparator circuits configured to compare data provided by the first set of registers with data provided by the second set of registers according to the row control registers, and an error detection circuit configured to compare results from four comparator circuits corresponding to two adjacent rows and two columns of the matrix of comparator circuits. A method that invokes the above mentioned apparatus is also disclosed herein, along with a computer program product corresponding to the method.Type: ApplicationFiled: January 21, 2015Publication date: July 21, 2016Inventors: James R. Cuffney, Timothy J. Koprowski, John G. Rell, JR., Patrick M. West, JR.
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Patent number: 9389865Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: GrantFiled: December 28, 2015Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, Jr.
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Patent number: 9389955Abstract: An apparatus for comparing strings comprises a first and a second set of input registers, a matrix of comparator circuits wherein rows of the matrix correspond to the first set of input registers and columns of the matrix correspond to the second set of input registers, a set of row control registers wherein each register corresponds to a row of the matrix of the comparator circuits, the matrix of comparator circuits configured to compare data provided by the first set of registers with data provided by the second set of registers according to the row control registers, and an error detection circuit configured to compare results from four comparator circuits corresponding to two adjacent rows and two columns of the matrix of comparator circuits. A method that invokes the above mentioned apparatus is also disclosed herein, along with a computer program product corresponding to the method.Type: GrantFiled: December 29, 2015Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: James R. Cuffney, Timothy J. Koprowski, John G. Rell, Jr., Patrick M. West, Jr.
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Publication number: 20160179468Abstract: Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.Type: ApplicationFiled: March 10, 2016Publication date: June 23, 2016Inventors: James R. Cuffney, John G. Rell, JR., Eric M. Schwarz, Patrick M. West, JR.
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Publication number: 20160117191Abstract: Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.Type: ApplicationFiled: October 28, 2014Publication date: April 28, 2016Inventors: Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, John G. Rell, JR., Timothy J. Slegel
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Publication number: 20160117192Abstract: Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.Type: ApplicationFiled: September 7, 2015Publication date: April 28, 2016Inventors: Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, John G. Rell, JR., Timothy J. Slegel
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Publication number: 20160092214Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.Type: ApplicationFiled: September 30, 2014Publication date: March 31, 2016Inventors: FADI Y. BUSABA, MICHAEL T. HUFFER, DAVID S. HUTTON, EDWARD T. MALLEY, JOHN G. RELL, Jr., ERIC M. SCHWARZ, AARON TSAI
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Publication number: 20160092216Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.Type: ApplicationFiled: September 1, 2015Publication date: March 31, 2016Inventors: FADI Y. BUSABA, MICHAEL T. HUFFER, DAVID S. HUTTON, EDWARD T. MALLEY, JOHN G. RELL, JR., ERIC M. SCHWARZ, AARON TSAI
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Patent number: 9201655Abstract: Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.Type: GrantFiled: March 19, 2008Date of Patent: December 1, 2015Assignee: International Business Machines CorporationInventors: Vimal M. Kapadia, Fadi Y. Busaba, Edward T. Malley, John G. Rell, Jr., Chung-Lung Kevin Shum
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Publication number: 20150261501Abstract: Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: James R. Cuffney, John G. Rell, JR., Eric M. Schwarz, Patrick M. West, JR.
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Publication number: 20150261504Abstract: Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.Type: ApplicationFiled: May 30, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: James R. Cuffney, John G. Rell, JR., Eric M. Schwarz, Patrick M. West, JR.
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Publication number: 20150261503Abstract: Embodiments relate to vectorized Galois field multiplication. An aspect includes a subdivision of first and second input operands into vector elements of equal sizes with multiple modes defined such that a base mode has a size corresponding to a smallest vector element size, which is a factor of a size of the first and second input operands, and a higher mode has a size that is a multiple of the base mode size. The vector elements of the first input operand are modified with a bit mask based on a size of the vector elements. The modified vector elements of the first input operand and the vector elements of the second input operand are input into a single hardware tree configured for subdivision into staggered subtrees a size of each of which being based on the base mode size.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: James R. Cuffney, John G. Rell, JR., Eric M. Schwarz, Patrick M. West, JR.
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Publication number: 20130339670Abstract: Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi Busaba, David Hutton, John G. Rell, JR., Chung-Lung K. Shum
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Patent number: 7971034Abstract: A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode.Type: GrantFiled: March 19, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: David S. Hutton, Michael Billeci, Fadi Y. Busaba, Brian R. Prasky, John G. Rell, Jr., Chung-Lung Kevin Shum, Charles F. Webb
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Patent number: 7962726Abstract: A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.Type: GrantFiled: March 19, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Edward T. Malley, Khary J. Alexander, Fadi Y. Busaba, Vimal M. Kapadia, Jeffrey S. Plate, John G. Rell, Jr., Chung-Lung Kevin Shum
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Patent number: 7949972Abstract: Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions.Type: GrantFiled: March 19, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Edward T. Malley, Fadi Y. Busaba, David S. Hutton, Christopher A. Krygowski, Jeffrey S. Plate, John G. Rell