Abstract: A method and apparatus for efficiently storing multiple data types in a computer's register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.

Abstract: A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.

Abstract: A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

Abstract: An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of execution units, executing an instruction of the first instruction set in response to a first counter, and executing at least one instruction of the second instruction set in response to at least a second counter, wherein the second counter is invoked by a branch instruction of the first instruction set.

Abstract: An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by the signals within the adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including art A/D converter for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator for producing a first set of complex I and Q components from the digital signal data stream and a guard segment length detector using the first set of I and Q components. It further includes an extractor for identifying and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including an A/D converter (52) for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator (54) for producing a first set of complex I and Q components from the digital data stream and a guard segment length detector (58) using the first set of I and Q components. It further includes an extractor (62) for extracting and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator (64) for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: Techniques for conserving power by controlling program execution in a convergence device comprising a battery or other power source and at least one processor. The processor is configured to perform processing operations associated with voice call communication functions and to perform processing operations associated with data communication functions, and is operative to execute critical programs and noncritical programs. The convergence device stores, for at least a given one of a plurality of noncritical programs associated with the data communication functions, an identifier of at least one alternate capacity program capable of performing substantially the same function as the given program but having a different power source capacity associated therewith.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: A dipole antenna for a wireless communication device, which includes a first conductive element superimposed on a portion of and separated from a second conductive element by a first dielectric layer. A first conductive via connects the first and second conductive elements through the first dielectric layer. The second conductive element is generally U-shaped. The second conductive element includes a plurality of spaced conductive strips extending transverse from adjacent ends of the legs of the U-shape. Each strip is dimensioned for a different center frequency ?0. The first conductive element may be replaced by a coaxial feed directly to the second conductive element.