Patents by Inventor John Halbert
John Halbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240116985Abstract: Among other things, the present disclosure provides various agents. In some embodiments, provided agents can bind to beta-catenin. In some embodiments, the present disclosure provides technologies for modulating beta-catenin functions. In some embodiments, the present disclosure provides technologies for preventing and/or treating conditions, disorders or diseases associated with beta-catenin. In some embodiments, the present disclosure provides designed amino acids which can provide improved properties and/or activities. In some embodiments, the present disclosure provides agents comprising such amino acids.Type: ApplicationFiled: July 22, 2021Publication date: April 11, 2024Inventors: Brian Halbert White, Yaguang Si, Martin Robert Tremblay, Deborah Gail Conrady, Yue-Mei Zhang, Ivan Tucker Jewett, Lorenzo Josue Alfaro-Lopez, Sarah Isabelle Cappucci, Zhi Li, John Hanney McGee
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Patent number: 9824743Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.Type: GrantFiled: May 3, 2017Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Bruce Querbach, Kuljit Bains, John Halbert
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Patent number: 9768148Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: GrantFiled: December 31, 2014Date of Patent: September 19, 2017Assignee: INTEL CORPORATIONInventors: Pete Vogt, Andre Schaefer, Warren Morrow, John Halbert, Jin Kim, Kenneth Shoemaker
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Publication number: 20170236575Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Applicant: Intel CorporationInventors: Bruce QUERBACH, Kuljit BAINS, John HALBERT
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Patent number: 9117544Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.Type: GrantFiled: October 31, 2013Date of Patent: August 25, 2015Assignee: Intel CorporationInventors: Kuljit Bains, John Halbert, Christopher Mozak, Theodore Schoenborn, Zvika Greenfield
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Publication number: 20150109871Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.Type: ApplicationFiled: December 17, 2013Publication date: April 23, 2015Inventors: Kuljit BAINS, John Halbert
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Publication number: 20150108660Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: December 31, 2014Publication date: April 23, 2015Inventors: Pete Vogt, Andre Schaefer, Warren Morrow, John Halbert, Jin Kim, Kenneth Shoemaker
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Patent number: 8971087Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: GrantFiled: December 2, 2011Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Pete Vogt, Andre Schaefer, Warren Morrow, John Halbert, Jin Kim, Kenneth Shoemaker
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Publication number: 20130272049Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: December 2, 2011Publication date: October 17, 2013Applicant: INTEL CORPORATIONInventors: Pete Vogt, Andre Schaefer, Warren Morrow, John Halbert, Jin Kim, Kenneth Shoemaker
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Patent number: 8238189Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.Type: GrantFiled: April 28, 2011Date of Patent: August 7, 2012Assignee: Intel CorporationInventors: Kuljit S. Bains, John Halbert
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Patent number: 8161356Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.Type: GrantFiled: March 28, 2008Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: Kuljit S. Bains, John Halbert, Michael W. Williams
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Publication number: 20110261636Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.Type: ApplicationFiled: April 28, 2011Publication date: October 27, 2011Inventors: Kuljit S. Bains, John Halbert
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Patent number: 7957216Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.Type: GrantFiled: September 30, 2008Date of Patent: June 7, 2011Assignee: Intel CorporationInventors: Kuljit S. Bains, John Halbert
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Publication number: 20100080076Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Kuljit S. Bains, John Halbert
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Publication number: 20090249169Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: KULJIT S. BAINS, John Halbert, Michael W. Williams
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Patent number: 7450456Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.Type: GrantFiled: May 10, 2007Date of Patent: November 11, 2008Assignee: Intel CorporationInventors: Sandeep Jain, David Wyatt, Jun Shi, Animesh Mishra, John Halbert, Melik Isbara
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Patent number: 7404055Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.Type: GrantFiled: March 28, 2006Date of Patent: July 22, 2008Assignee: Intel CorporationInventors: Kuljit Bains, John Halbert, Greg Lemos, Randy Osborne
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Patent number: 7349233Abstract: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.Type: GrantFiled: March 24, 2006Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Kuljit S. Bains, John Halbert
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Patent number: 7350016Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.Type: GrantFiled: January 10, 2006Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Kuljit S. Bains, Herbert Hum, John Halbert
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Publication number: 20080056047Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.Type: ApplicationFiled: October 31, 2007Publication date: March 6, 2008Inventors: Sandeep Jain, Animesh Mishra, John Halbert