Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: A cooler having a unitary construction including a channel portion including a plurality of fins on a base, the plurality of fins defining a plurality of microchannels therebetween, a tapered opening formed in a set of the plurality of fins, a manifold portion disposed on an edge portion of the base, the manifold portion including an inlet port and an outlet port disposed above the tapered opening in the plurality of fins, and a separator sheet including at least two elongated openings disposed between the channel portion and the manifold portion.

Abstract: A cooler includes a base layer, a cooling layer including at least one inlet slot and at least one outlet slot for flowing a coolant across a cooling structure including a plurality of staggered fins arranged in rows and columns, wherein fins of adjacent columns are staggered, and at least one manifold layer disposed on the cooling layer for flowing the coolant from a cooler inlet to the at least inlet slot and from the at least one outlet slot to a cooler outlet, the at least one manifold layer having a top layer comprising the cooler inlet and the cooler outlet.

Abstract: A cooler having a unitary construction including a channel portion including a plurality of fins on a base, the plurality of fins defining a plurality of microchannels therebetween, a tapered opening formed in a set of the plurality of fins, a manifold portion disposed on an edge portion of the base, the manifold portion including an inlet port and an outlet port disposed above the tapered opening in the plurality of fins, and a separator sheet including at least two elongated openings disposed between the channel portion and the manifold portion.

Abstract: A cooler having a unitary construction including a channel portion including a plurality of fins on a base, the plurality of fins defining a plurality of microchannels therebetween, a tapered opening formed in a set of the plurality of fins, a manifold portion disposed on an edge portion of the base, the manifold portion including an inlet port and an outlet port disposed above the tapered opening in the plurality of fins, and a separator sheet including at least two elongated openings disposed between the channel portion and the manifold portion.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: Apparatus and methods are provided for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.

Abstract: A cooler having a unitary construction including a channel portion including a plurality of fins on a base, the plurality of fins defining a plurality of microchannels therebetween, a tapered opening formed in a set of the plurality of fins, a manifold portion disposed on an edge portion of the base, the manifold portion including an inlet port and an outlet port disposed above the tapered opening in the plurality of fins, and a separator sheet including at least two elongated openings disposed between the channel portion and the manifold portion.

Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.

Abstract: A cooler includes a base layer, a cooling layer including at least one inlet slot and at least one outlet slot for flowing a coolant across a cooling structure including a plurality of staggered fins arranged in rows and columns, wherein fins of adjacent columns are staggered, and at least one manifold layer disposed on the cooling layer for flowing the coolant from a cooler inlet to the at least inlet slot and from the at least one outlet slot to a cooler outlet, the at least one manifold layer having a top layer comprising the cooler inlet and the cooler outlet.

Abstract: Apparatus and methods are provided for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: An electronic apparatus includes first and second level package structures and an LGA (land grid array) interposer. The first level package structure includes a package substrate, one or more integrated circuit chips mounted on a first surface of the package substrate, and a first pattern of I/O contacts with pitch P1 formed on a second surface of the package substrate opposite the first surface. The second level package structure includes a second pattern of I/O contacts with pitch P2, wherein P2 is not equal to P1. The LGA interposer is disposed between the first and second level package structures and provides space transform electrical interconnections between the first second patterns of I/O contacts, and further includes a dummy contact formed on at least a first or second surface of the LGA interposer and aligned to an LGA contact on an opposing surface of the LGA interposer.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: Apparatus and methods are provided for microchannel cooling of electronic devices such as IC chips, which enable efficient and low operating pressure microchannel cooling of high power density electronic devices. Apparatus for microchannel cooling include integrated microchannel heat sink devices and fluid distribution manifold structures that are designed to provide uniform flow and distribution of coolant fluid and minimize pressure drops along coolant flow paths.