Abstract: The thickness of a selected layer in an epitaxial heterojunction transistor is initially set to the exact desired value upon its formation, preferably by molecular beam epitaxy, and its thickness is left virtually unaltered during the rest of the fabrication process. Means are provided to prevent alteration of this thickness during subsequent exposure of the selected layer.

Abstract: A field-effect transistor (FET) and a corresponding method for its fabrication, the transistor having a source and a gate located at opposite faces of an active channel region formed in a substrate, the source being substantially shorter in effective length than the gate and located symmetrically with respect to the gate. The transistor also has two drains, located one at each end of the channel region, and charge carriers flow from the source to the drains in two paths, under control of the same gate. Electrical contact with the source is made from beneath the substrate, while contact with the gate and drains is made from above. The resulting device has a large incremental transconductance and relatively small parasitic impedances, and therefore can operate at much higher frequencies than conventional FET's.

Abstract: A two-gate non-coplanar field-effect transistor and a method for its fabrication. An active semiconductor layer is formed over a stop-etch layer on a substrate of semi-insulating material, such as gallium arsenide, and a via hole is formed from the opposite face of the substrate, through to the stop-etch layer. The via hole is metallized and located from the active-layer side of the device using an electron-beam technique. A two-element gate structure is then formed over the active layer, in approximate alignment with the via hole. Then a source region is ion-implanted into the active layer and into the stop-etch layer, using the positions of the gate elements to self-align the source. Drain contact regions are also formed in the active layer by ion implantation. Contact between the source region and the metallized via hole does not depend on accurate and uniform etching of the via hole.

Abstract: A field-effect transistor in which the gate and source are positioned on opposite faces of a substrate, and a method for its fabrication. In the method, a stop-etch buffer layer and an active semiconductor layer are successively formed by molecular beam epitaxy on a first face of a substrate of semi-insulating material, such as gallium arsenide. A source via hole is etched from the opposite face of the substrate, using a first etchant that does not react with the buffer layer, and extended through the buffer layer with a second etchant that does not react with the active layer. After metalization of the source via hole, electron beam lithography techniques are used to determine its location as viewed from the first face of the substrate. Then a mesa area is formed from the active layer, and drain and gate areas are defined in precise relation to the source via hole, and are metalized.