Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: An apparatus and method for cutting a surgical suture at a first and second different location along its length. The apparatus having a first and a second cutting die with channels for receiving at least a portion of the cross-section of the surgical suture at each location. Each of the first and second cutting dies respectively is provided with an opposing cutting die to further restraint the suture. A blade is also provided at each cutting location for cutting the suture at a point adjacent to the respective cutting dies when the suture is restrained between the sets of dies.

Abstract: A surgical suture comprised of a first thermally formed tip portion having a first length which is adjacent to a body portion having a second length. The first thermally formed tip portion has a generally uniform cross-section perpendicular to the first length, while the body portion has a varying cross-section which corresponds to a distribution of different cross-sectional sizes along the second length. The generally uniform cross-section of the first thermally formed tip portion has an average cross-sectional size that is less than the average of the different cross-sectional sizes along the second length.

Abstract: A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch circuit to offset the output signal. A phase adjustment adjusts the phase relationship of the first and second signals so that the offset output signal is representative of a null condition. The switch circuit preferably is a Gilbert multiplier having a current source, an impedance means, and a transistor circuit connected between the current source and the impedance means. The transistor circuit has first and second inputs for receiving the first and second signals. The reference signal is input between the transistor circuit and the impedance means and is connected to an output. The output provides the output signal having a value based on the reference signal and the phase relationship of the first and second signals.

Abstract: A system for writing servo information to a plurality of magnetic discs in a servo write mode, and for writing data to the plurality of magnetic discs in a data write mode in disclosed. The system includes a servo binary input buffer for receiving a mode signal and for directing the write signal based upon the mode signal. A first plurality of switches, coupled to the servo binary input buffer and to a disc select buffer, directs the write signal to a selected portion of a plurality of write heads. A second plurality of switches, coupled to the first plurality of switches, to the plurality of write heads, and to a head select buffer, supplies the write signal to one write head in the selected portion of the plurality of write heads during the data write mode, and supplies the write signal to one half of the write heads in the selected portion of the plurality of write heads during the servo write mode.

Abstract: A logic translating buffer for low voltage operation for receiving a TTL compatible signal and providing a current mode logic signal. The logic translating buffer includes an emitter coupled differential pair of NPN transistors with the common emitters each being connected to a current source. One of the transistors of the differential pair has a constant voltage bias applied to the base thereof that is equal to the sum of a forward biased PN junction, a forward biased Schottky diode, and the voltage drop across a first resistor. The other transistor of the differential pair is provided a signal that is representative of the logic level input to the translating buffer. A clamping transistor is provided for keeping the other transistor of the differential pair from saturating.

Abstract: The present invention is an improved current mirror circuit. This improved current mirror circuit includes first and second transistors of the same conductivity type and have bases connected together. The first transistor is connected between a first supply terminal and an input terminal. The second transistor is connected between a first supply terminal and an output terminal. Included is a feedback circuit for providing a voltage feedback between the input terminal and the bases of the first and second transistors. Also included is a bias circuit for providing a bias current to the feedback circuit that is based on the input current.

Abstract: A magnetic head swing clamp configured for interconnection with a read/write preamplifier of the type including a read differential transistor pair connected to an inductive head. The collectors of the transistors in the read differential transistor pair provide first and second read output signals at first and second read output terminals for connection to a read amplifier. The magnetic head swing clamp comprises a reference voltage generator which produces first and second reference voltage levels at first and second reference voltage output terminals. Positive and negative voltage clamps are electrically connected to the first and second reference voltage output terminals, respectively, and to the first and second read output terminals. The positive and negative voltage clamps clamp voltage swings in the first and second read output signals as functions of the first and second reference voltage levels.

Abstract: An amplifier includes first and second transistors each of which has a conduction path, with first and second conduction path terminals, and a control terminal for controlling conduction through the conduction path. The amplifier also includes a current source and voltage reference terminal for being coupled to a voltage reference. A first Schottky diode has an intrinsic series resistance and is coupled between the second conduction path terminal of the first transistor and the current source. A second Schottky diode has an intrinsic series resistance and is coupled between the second conduction path terminal of the second transistor and the current source.

Abstract: A read/write preamplifier configured for interconnection with a magnetic head through head contacts. The preamplifier includes a write control switching circuit electrically connected between first and second supply terminals and connected to the head contacts, for controlling current flow through the magnetic head. The switching circuit includes at least one transistor. A first PNP-type transistor is connected between the first supply terminal and the at least one transistor of the write control switching circuit, for controlling current flow to the write control switching circuit so as to cause the switching circuit to be driven between selected and unselected states. A PNP-type transistor bias circuit includes a mode-controlled current sink coupled between the first and second supply terminals and to the first PNP-type transistor.

Abstract: A translation circuit provides an output referenced to ground in response to either an ECL input or a TTL input. ECL or TTL supply voltages are selectively applied to first, second, third and fourth supply voltage terminals in accordance with the type of input signal received.

Abstract: A bit switch is provided for use in a digital-to-analog converter for providing a bit current to a summing bus. A first differential pair of switching devices are responsive to a digital input signal and provide first and second output signals to a second differential pair of switching devices that provide the bit current. First and second drive circuits are coupled between the first and second differential pair of switching devices for respectively slowing down the voltage transition of the first and second output signals for reducing glitches in the bit current.

Abstract: A voltage reference circuit for providing a temperature compensated voltage at an output thereof comprise a pair of transistor operated at different current densities for producing a first and second voltages having complementary temperature coefficients and circuitry for combining the two voltages to produce the temperature compensated voltage. A pair of load resistors are connected to the collectors of the two transistors for sourcing currents thereto and a feedback circuit, including a differential amplifier coupled to the respective collectors, provides a feedback signal for adjusting the potential on the bases thereof to maintain different current densities in the two transistors. A bias circuit operates in conjunction with the differential amplifier to bias the same in a balanced operating state whenever the currents in the transistors are substantially equal.

Abstract: The input voltage signals to a comparison circuit may vary between levels substantial equal to the first and second supply voltages (e.g. typically 5 volts and ground). A first transistor circuit is coupled to a current mirror circuit and to an output node for supplying a mirrorable current to the current mirror circuit which in turn reduces the voltage at the output node when the first input voltage approaches the upper supply voltage, and supplies a current to the output to increase the voltage thereat when the second input approaches the upper supply voltage. A second transistor circuit is also coupled to the current mirror and to the output for supplying a mirrorable current to the current mirror means so as to reduce the voltage at the output when the second input voltage approaches ground, and supplies current to the output to increase the voltage thereat when the first input voltage approaches ground.

Abstract: A circuit for use with interface systems for providing a threshold setting function wherein the system can be made to interface with T.sup.2 L or CMOS logic with either 5 or 15 volt power supply capabilities. The circuit comprises a pair of matched resistors coupled in series to one another. The first one of the resistors is returned to a select terminal via a first pair of diodes. The second resistor is returned to a terminal at which may be supplied a ground reference potential via a second pair of diodes. A source of current is provided that is coupled to the interconnection of the second resistor with the second pair of diodes. A threshold output is provided to the interface system at the interconnection between the serially connected resistors.

Abstract: A bit switch for use in a digital-to-analog converter comprises three differential pairs of transistors. The first pair receives a digital input signal and a reference voltage signal. The second pair switches the bit current to either an output bus or to ground depending upon the state of the input signal. A third differential pair of transistors is coupled between the first and second pairs for minimizing adverse effects of fast input transitions and parasitic capacitance.

Abstract: A current drive source circuit for providing current drive to a plurality of loads coupled thereto for reducing effects of power supply variations on the loads. The current drive source includes a reference circuit for producing a reference bias potential for biasing a load transistor. An internal current source comprising a split dual-collector PNP transistor provides collector current to the load transistor and also a feedback signal path to the emitter of the load transistor, which emitter electrode is coupled via a resistor to a ground terminal. The output of the current drive source is provided at the base electrode of the split dual-collector transistor.

Abstract: A monolithic amplifier circuit including a differential stage, a differential-to-single ended converter stage, a bias circuit and complementary push-pull output transistors is disclosed. The bias circuit is comprised of a current supply, two semiconductor bias devices and two current sinks. The junctions of the bias devices are connected in series across the junctions of the complementary output transistors to provide bias and to compensate for temperature and process variations in the output transistors. One of the bias devices and one of the current sinks are connected in one parallel path and the other bias device and the other current sink are connected in another parallel path through which most of the current from the current supply flows. This parallel connection enables utilization of minimum geometry bias devices in addition to facilitating precise and predictable control of the bias voltages and currents.

Abstract: Combining a differential PNP transistor pair for receiving external digital signals with an NPN output transistor in an I.sup.2 L configuration connected to the output of the differential pair provides a simple, high-speed, and versatile digital logic to I.sup.2 L interface circuit. The interface circuit is applicable to almost any digital logic series and also to analog inputs as they provide inputs into I.sup.2 L circuitry.

Abstract: There is disclosed a trim network suitable to be utilized in monolithic circuits and a method of trimming thereof to improve performance of the circuits to achieve greater yields. The network comprises at least one monolithic resistor connected across a known voltage potential and including a plurality of contacts thereon defining incremental resistances therebetween. The contacts are coupled to a common terminal via a plurality of metallic links. A desired output voltage is derived at the common terminal by open circuiting all of the links but a desired one. The voltage appearing at the common terminal can then be used for trimming a parameter of the monolithic circuit to improve the performance thereof.