Patents by Inventor John J. Vaglica
John J. Vaglica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7415558Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.Type: GrantFiled: December 14, 2006Date of Patent: August 19, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Arnaldo R. Cruz, John J. Vaglica, William C. Moyer, Tuongvu V. Nguyen
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Patent number: 7362645Abstract: Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).Type: GrantFiled: September 30, 2004Date of Patent: April 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, John J. Vaglica, William C. Moyer, Ryan D. Bedwell
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Patent number: 7278062Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.Type: GrantFiled: January 9, 2003Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, Brian M. Millar, John J. Vaglica
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Patent number: 7237149Abstract: A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality of registers (26) is sourcing the debug information. A user-determinable enable and disable mechanism that is correlated to some or all of the registers sourcing the debug information specifies whether to enable or disable the providing of the debug information. In one form a single bit functions as the mechanism for each correlated register. Debug operations including breakpoints, tracing, watchpoints, halting, event counting and others are qualified to enhance system debug. The registers may be included in a programmer's model and can be compliant with one or more industry debug related standards.Type: GrantFiled: February 25, 2005Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, John J. Vaglica
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Patent number: 7181188Abstract: A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.Type: GrantFiled: March 23, 2004Date of Patent: February 20, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Mieu Van Vu, Christopher K. Chun, Arthur M. Goldberg, David J. Hayes, Charbel Khawand, Jianping Tao, John J. Vaglica
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Patent number: 7047350Abstract: A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.Type: GrantFiled: October 10, 2003Date of Patent: May 16, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Mark E. Elledge, John J. Vaglica, Sreedharan Bhaskaran, Allen Guoyuan Deng
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Patent number: 6973540Abstract: In a multi-way cache, a method for selecting N ways available for replacement includes providing a plurality of rulesets where each one of the plurality of rulesets specifies N ways in the cache that are available for replacement (where N is equal to or greater than zero). The method further includes receiving an access address, and using at least a portion of the access address to select one of the plurality of rulesets. The selected one of the plurality of rulesets may then be used to select N ways in that cache that are available for replacement. One embodiment uses the high order bits of the access address to select a ruleset. An alternate embodiment uses at least a portion of the access address and a ruleset selector control register to select the ruleset. Yet another embodiment uses the access address and address range comparators to select the ruleset.Type: GrantFiled: July 25, 2003Date of Patent: December 6, 2005Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, John J. Vaglica
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Patent number: 6917555Abstract: Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.Type: GrantFiled: September 30, 2003Date of Patent: July 12, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Ryan D. Bedwell, Christopher K. Y. Chun, Qadeer A. Qureshi, John J. Vaglica
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Publication number: 20040139372Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Inventors: William C. Moyer, Michael D. Fitzsimmons, Brian M. Millar, John J. Vaglica
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Patent number: 6751724Abstract: Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.Type: GrantFiled: April 19, 2000Date of Patent: June 15, 2004Assignee: Motorola, Inc.Inventors: William C. Moyer, Jeffrey W. Scott, James S. Thomas, John H. Arends, John J. Vaglica
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Patent number: 6167484Abstract: A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.Type: GrantFiled: May 12, 1998Date of Patent: December 26, 2000Assignee: Motorola, Inc.Inventors: John Mark Boyer, William Clayton Bruce, Jr., Grady Lawrence Giles, Thomas K. Johnston, Bernard J. Pappert, John J. Vaglica
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Patent number: 6125404Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.Type: GrantFiled: April 17, 1998Date of Patent: September 26, 2000Assignee: Motorola, Inc.Inventors: John J. Vaglica, Paul McAlinden, Oded Norman, Moshe Refaeli, Yoram Salant, Thomas E. Oberhauser, Arvind Singh Arora
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Patent number: 5717931Abstract: A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.Type: GrantFiled: December 20, 1994Date of Patent: February 10, 1998Assignee: Motorola, Inc.Inventors: Adi Sapir, Ilan Pardo, James B. Eifert, Wallace B. Harwood, III, John J. Vaglica, Danny Shterman
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Patent number: 5448744Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset.Type: GrantFiled: November 6, 1989Date of Patent: September 5, 1995Assignee: Motorola, Inc.Inventors: James B. Eifert, John J. Vaglica, James C. Smallwood, Mark W. McDermott, Hiroyuki Sugiyama, William P. LaViolette, Bradley G. Burgess
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Patent number: 5204957Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.Type: GrantFiled: September 30, 1992Date of Patent: April 20, 1993Assignee: MotorolaInventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
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Patent number: 5084814Abstract: A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.Type: GrantFiled: October 30, 1987Date of Patent: January 28, 1992Assignee: Motorola, Inc.Inventors: John J. Vaglica, Jay A. Hartvigsen, Rand L. Gray
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Patent number: 4942522Abstract: A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.Type: GrantFiled: August 19, 1988Date of Patent: July 17, 1990Assignee: Motorola, Inc.Inventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
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Patent number: 4926319Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.Type: GrantFiled: August 19, 1988Date of Patent: May 15, 1990Assignee: Motorola Inc.Inventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica