Abstract: Certain aspects of the present disclosure generally relate to methods of fabricating integrated circuits. An example method generally includes forming a first cavity in a first layer disposed above a second layer and filling at least a portion of the first cavity with a dielectric material disposed above the second layer. The method further includes forming a second cavity in the dielectric material such that the dielectric material remaining in the first cavity is disposed on (e.g., conforms to) lateral surfaces of the first layer in the first cavity and forming a dielectric spacer comprising a segment of the remaining dielectric material in the first cavity. The method also includes forming a first conductor, in the first layer or the second layer, that is laterally spaced from a second conductor based at least in part on a width of the dielectric spacer.

Abstract: Aspects of the disclosure are directed to super via integration. In accordance with one aspect, an apparatus with super via integration in an integrated circuit including a first metal layer; a second metal layer, wherein the second metal layer is adjacent to the first metal layer; a third metal layer, wherein the third metal layer is adjacent to the second metal layer and is non-adjacent to the first metal layer; and a super via interconnecting the first metal layer and the third metal layer through a dielectric material, wherein the super via is filled with a selective metal.

Abstract: Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel and a first set of work function layer. The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel and a second set of work function layer. The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.

Abstract: Middle-of-line (MOL) complementary power rail(s) in integrated circuits (ICs) for reduced semiconductor device resistance, and related methods are disclosed. In exemplary aspects, to reduce or mitigate an increase in resistance in the cell power rails in the IC, a complementary power rail(s) is formed in a MOL layer(s) of the IC and coupled to cell power rail(s) formed in a metal layer in a front-end-of-line (FEOL) layer in the IC. In exemplary aspects, the MOL layer(s) in which the complementary power rail is formed is in a layer below the metal layer in the FEOL layer in which the cell power rail is formed. The complementary power rail has the effect of reducing the resistance of the cell power rail, and thus has the effect of reducing the resistance of FET(s) coupled to the cell power rail thereby increasing performance.

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.

Abstract: Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

Abstract: Systems and methods for dummy gate tie-offs in a self-aligned gate contact (SAGC) cell are disclosed. In particular, exemplary aspects contemplate a two-part etching process to remove hardmasks formed from different materials from adjacent elements. A metal fill material may then be used to tie off the adjacent elements. The use of the two-part etching process allows SAGC techniques to be used for a first portion of a cell while still providing a technique to allow a tie-off in a second portion of the cell. The tie-off may be used with a dummy gate to provide isolation between cells.

Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

Abstract: Semiconductor devices employing reduced area conformal contacts for reducing parasitic capacitance and improving performance, and related methods are disclosed. The area of the source/drain contacts for providing an electrical contract to a source/drain is reduced in size to reduce parasitic capacitance between a gate and the source/drain contacts for improved performance. To mitigate or avoid increase in contact resistance between the source/drain contacts and source/drain, a conformal contact layer of a desired thickness is disposed adjacent to the source/drain to reduce the source/drain contact resistance. Thus, the source/drain contacts may only have to extend down adjacent to an upper region of the source/drain to still achieve a desired, lower contact resistance with the source/drain contacts, which results in a reduced area source/drain contact for reducing parasitic capacitance.

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.