Abstract: An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit comprises at least one shunt circuit operable to shunt current related to an over-voltage condition and at least one series element operably coupled to the shunt element. The shunt element and series element in combination provide electrostatic discharge protection for the RF signal processing circuit elements on the integrated circuit and also provide a matched input impedance for an incoming RF signal. Various alternate embodiments of the electrostatic-discharge/impedance-matching circuit include first and second shunt elements and a series element operably connected in combination to provide optimal electrostatic discharge protection and impedance matching.

Abstract: Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a gate of a first transistor to a first differential input of the buffer and coupling a gate of a second transistor to a second differential input of the buffer. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer, where the common mode output of the DC voltage source may be coupled to the gate of the first transistor and the gate of the second transistor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Abstract: Methods and systems for increasing gain for an electric circuit are disclosed herein. Aspects of the method may comprise receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Abstract: Methods and systems for increasing an amplifier circuit's Q factor are disclosed herein. The method may comprise coupling a first LC tank to a source of a single switching transistor and coupling a second LC tank to a drain of the single switching transistor. A gate of the single switching transistor may be controlled by an amplifier core coupled to the first LC tank and the second LC tank. A resistance of the first LC tank and the second LC tank may be decreased by about one half, which increases the Q factor by about two. The gate of the single switching transistor may be controlled by a control signal generator coupled to the amplifier core. The first LC tank and/or the second LC tank may be tuned to a frequency of about 3.4 GHz to 4 GHz. The single switching transistor may comprise an NMOS transistor.

Abstract: Methods and systems for increasing gain for an electric circuit may include receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Abstract: Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a gate of a first transistor to a first differential input of the buffer and coupling a gate of a second transistor to a second differential input of the buffer. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer, where the common mode output of the DC voltage source may be coupled to the gate of the first transistor and the gate of the second transistor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

Abstract: Methods and systems for increasing an amplifier circuit's Q factor are disclosed herein. The method may comprise coupling a first LC tank to a source of a single switching transistor and coupling a second LC tank to a drain of the single switching transistor. A gate of the single switching transistor may be controlled by an amplifier core coupled to the first LC tank and the second LC tank. A resistance of the first LC tank and the second LC tank may be decreased by about one half, which increases the Q factor by about two. The gate of the single switching transistor may be controlled by a control signal generator coupled to the amplifier core. The first LC tank and/or the second LC tank may be tuned to a frequency of about 3.4 GHz to 4 GHz. The single switching transistor may comprise an NMOS transistor.

Abstract: Methods and systems for processing signals for a multiband radio are disclosed herein. Aspects of the method may comprise dividing an input signal generated by an oscillator used to generate signals for each of a plurality of bands for the multiband radio. A feedback loop reference signal may be generated from the input signal and a coarse calibration signal may be generated from the feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal. The input signal may be buffered and/or divided by a divide by four (4) divider circuit. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The generated feedback loop reference signal may be buffered and/or divided prior to the calibration. The coarse calibration signal may comprise a 7-bit calibration signal. A fine calibration signal may be generated from the feedback loop reference signal.

Abstract: The radio receiver includes a low noise amplifier that amplifies a received signal to one of three different gain settings. One gain setting is maximum amplification, a second gain setting is 6 dB below maximum amplification and a third gain setting is 32 dB below maximum amplification. In the case of the third setting, the low noise amplifier actually attenuates the received signal by 6 dB. The radio receiver includes a pair of received signal strength indicators that provide received signal strength indications to logic circuitry. Responsive to the received signal strength indications, the logic circuitry generates control commands to the low noise amplifier to prompt it to amplify at one of the three specified levels. Generally, if the received signal has a gain level that exceeds a specified threshold, the low noise amplifier actually attenuates the received signal; otherwise, the level of amplification that is actually provided is a function of the presence of intermodulation interference.

Abstract: The radio receiver includes a low noise amplifier that amplifies a received signal to one of three different gain settings. One gain setting is maximum amplification, a second gain setting is 6 dB below maximum amplification and a third gain setting is 32 dB below maximum amplification. In the case of the third setting, the low noise amplifier actually attenuates the received signal by 6 dB. The radio receiver includes a pair of received signal strength indicators that provide received signal strength indications to logic circuitry. Responsive to the received signal strength indications, the logic circuitry generates control commands to the low noise amplifier to prompt it to amplify at one of the three specified levels. Generally, if the received signal has a gain level that exceeds a specified threshold, the low noise amplifier actually attenuates the received signal; otherwise, the level of amplification that is actually provided is a function of the presence of intermodulation interference.