Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract: A prosthetic heart valve provided herein can include at least two leaflets being secured together along aligned edges thereof by a stitch of a single thread. The stitch includes at least one loop extending through a first aperture, around the aligned edges, and back through the first aperture.

Abstract: A prosthetic heart valve provided herein can include at least one leaflet having a body portion and two opposite sleeve portions. The body portion can be defined by at least two side edges adjacent each sleeve portion. The at least one leaflet can define at least one notch between at least one of the two side edges and the adjacent sleeve portion, or at least one aperture positioned adjacent at least one side edge and an adjacent sleeve portion.

Abstract: The invention provides a new use of adenosine analogs for the treatment of pain through activation of neurokinin 1 (NK1) receptor signaling pathway, thereby inducing the activation of activation of M-type potassium channel to induce outward currents. A method and pharmaceutical composition for treating pain comprising an adenonsine analog that activates NK1 receptor signaling, thereby inducing outward current are also provided.

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract: A single word and multi-word term integrating system and a method thereof are disclosed, wherein a user uses an input unit to continuously input pinying codes for the system to find combinations of the pinying codes to provide word candidates for the user to choose, wherein the word candidates can be combined into a phrase or a sentence; when the inputted pinying codes are too long or incomplete, there might be a false prediction of a word or a sentence due to an incorrect combination of pinying codes; consequently, the system forcibly determines the pinying codes to be regarded as a single word and does not combine them with the follow-up pinying codes; then the system uses a full sentence prediction result display unit for the user to choose a correct word, thereby improving prediction accuracy.

Abstract: A system and methods are provided for removal of undesired portions of a fruit or vegetable, such as removal of calyxes from strawberries before they are flash frozen. An automated process for high-throughput fruit or vegetable calyx removal includes a loading system, an identification system, and a removal system. The loading system is configured to transport the fruit or vegetable through the automated process. The loading system may also orient the fruits or vegetables along an axis of the fruit and or align the fruit or vegetables in a desired pattern, orientation, and/or arrangement. The identification system is configured to locate the calyx and determines calyx position data and an optimal cutting path for individual fruit. The removal system uses data received from the identification system to separate the calyx from the fruit or vegetable.

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract: A prosthetic heart valve provided herein can include at least one leaflet having a body portion and two opposite sleeve portions. The body portion can be defined by at a least two side edges adjacent each sleeve portion. The at least one leaflet can define at least one notch between at least one of the two side edges and the adjacent sleeve portion, or at least one aperture positioned adjacent at least one side edge and an adjacent sleeve portion.

Abstract: A tubular seal for a prosthetic heart valve includes an elastomeric polymer matrix and a plurality of non-elastic fibers retained within the matrix. The non-elastic fibers can be arranged in the elastomeric polymer matrix to allow the tubular seal to stretch in axial and radial directions.

Abstract: A prosthetic heart valve provided herein can include at least two leaflets being secured together along aligned edges thereof by a stitch of a single thread. The stitch includes at least one loop extending through a first aperture, around the aligned edges, and back through the first aperture.

Abstract: A process for automated high-throughput fruit or vegetable calyx removal includes a material handling system, a vision system, and a cutting system. The material handling system is capable of transporting the fruit or vegetable through the automated process. The material handling system may also orient the fruits or vegetables along an axis of the fruit and or align the fruit or vegetables in a desired pattern, orientation, and/or configuration. The vision system identifies the calyx and determines calyx position data and optimal cutting angle for individual fruit. The cutting system uses data received from the vision system to automatically remove the calyx from the fruit or vegetables.

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

Abstract: An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.

Abstract: A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (?) 1017 atoms/cm3 with a boron doping or n-type doping concentration of between 1×1012 cm?3 and 5×1014 cm?3. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (?) to 30 minutes.

Abstract: An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.

Abstract: The disclosure provides a new use of adenosine analogs for the treatment of pain through activation of neurokinin 1 (NK1) receptor signaling pathway, thereby inducing the activation of M-type potassium channel to induce outward currents. A method and pharmaceutical composition for treating pain comprising an adenonsine analog that activates NK1 receptor signaling, thereby inducing outward current are also provided.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.