Abstract: In a design structure for allocating a plurality of parts of a computational system to a computational job, a set of requirements necessary to execute the job is determined. A set of parts of the plurality of parts is assembled so that the set of parts is capable of meeting the set of requirements and so that a part is added to the set of parts based on a determination that the addition of the part will minimize power consumption by the set of parts. The set of parts are caused to execute the job.

Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: A method, apparatus and program product enable memory compression for a system including processor with directly attached memory. A memory expander microchip facilitates memory compression while attached to a processor. The memory expander microchip may provide additional bandwidth and memory capacity for the system to enable memory compression in a manner that does not burden the attached processor or associated operating system. The processor may store uncompressed data in its lower latency, directly attached memory, while the memory attached to the memory expander may store either or both compressed and uncompressed data.

Abstract: A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.

Abstract: A method, apparatus and program product enable associativity operations for system including a processor having directly attached memory. A memory expander microchip facilitates concurrent memory access while attached to a processor. Associativity may have particular application in the context of accessing a data cache, which may be present on the memory expander microchip or memory in communication with the microchip. The memory expander microchip and associated memory channels may provide additional bandwidth and memory capacity for the system to enable associativity in a manner that does not burden the attached processor or associated operating system. Bandwidth and memory may be dynamically allocated to optimize associativity and applicable operating ratios.

Abstract: A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a data unit with a high usage frequency is stored in a memory location with a low latency.

Abstract: An apparatus for disabling a circuit when the circuit is in a first preselected condition includes a critical element that has an enable state and a disable state. The critical element is configured in relation to the circuit such that the circuit cannot operate normally if the critical element is in the disable state. A trigger generates a state signal that causes the critical element to enter the disable state when a comparison of a current condition to a stored value indicates that the circuit is in the first preselected condition. In a method of controlling operation of a circuit, a current condition is sensed. Whether the current condition corresponds to a stored value is determined. If the current condition corresponds to the stored value, then a critical element is caused to enter a disable state so that the circuit is prevented from operating normally.

Abstract: A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.

Abstract: A first method for efficient memory usage includes (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.

Abstract: In a design structure for allocating a plurality of parts of a computational system to a computational job, a set of requirements necessary to execute the job is determined. A set of parts of the plurality of parts is assembled so that the set of parts is capable of meeting the set of requirements and so that a part is added to the set of parts based on a determination that the addition of the part will minimize power consumption by the set of parts. The set of parts are caused to execute the job.

Abstract: A method, an apparatus and a program product may enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips may include non-volatile memory to provide additional memory bandwidth and capacity while in communication with the processor. The uncompressed data region may be implemented with standard high speed dynamic random access memory. The less frequently accessed compressed data region may be implemented with non-volatile memory to leverage its benefits of higher density, more capacity, and lower power compared to DRAM. Memory and bandwidth allocation between may be dynamically adjusted.

Abstract: A method, apparatus and program product enable associativity operations for system including a processor having directly attached memory. A memory expander microchip facilitates concurrent memory access while attached to a processor. Associativity may have particular application in the context of accessing a data cache, which may be present on the memory expander microchip or memory in communication with the microchip. The memory expander microchip and associated memory channels may provide additional bandwidth and memory capacity for the system to enable associativity in a manner that does not burden the attached processor or associated operating system. Bandwidth and memory may be dynamically allocated to optimize associativity and applicable operating ratios.

Abstract: A method, apparatus and program product enable memory compression for a system including processor with directly attached memory. A memory expander microchip facilitates memory compression while attached to a processor. The memory expander microchip may provide additional bandwidth and memory capacity for the system to enable memory compression in a manner that does not burden the attached processor or associated operating system. The processor may store uncompressed data in its lower latency, directly attached memory, while the memory attached to the memory expander may store either or both compressed and uncompressed data.

Abstract: A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.

Abstract: A method, computer program product and computer system for assigning computing resources in a computer system to solve multiple problems where tolerances to the problems are countable and have pre-set thresholds, and solutions to the problems share resources exclusively. The method, computer program product and system include counting the tolerances using at least one counter, assigning resources to solve a problem if the tolerance to the problem is higher than a first pre-set threshold, and reassigning resources to solve a second problem if the tolerance to the second problem is higher than a second pre-set threshold. The method, computer program product and system can also adopt an alternative solution that does not share resources exclusively with a current solution to solve the problems.

Abstract: A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.

Abstract: A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract: A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.