Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved.

Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus.

Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

Abstract: A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

Abstract: A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract: A design structure for controlling computer-readable memory includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.

Abstract: In a method of allocating a plurality of parts of a computational system to a computational job, a set of requirements necessary to execute the job is determined. A set of parts of the plurality of parts is assembled so that the set of parts is capable of meeting the set of requirements and so that a part is added to the set of parts based on a determination that the addition of the part will minimize power consumption by the set of parts. The set of parts are caused to execute the job.

Abstract: An apparatus for disabling a circuit when the circuit is in a first preselected condition includes a critical element that has an enable state and a disable state. The critical element is configured in relation to the circuit such that the circuit cannot operate normally if the critical element is in the disable state. A trigger generates a state signal that causes the critical element to enter the disable state when a comparison of a current condition to a stored value indicates that the circuit is in the first preselected condition. In a method of controlling operation of a circuit, a current condition is sensed. Whether the current condition corresponds to a stored value is determined. If the current condition corresponds to the stored value, then a critical element is caused to enter a disable state so that the circuit is prevented from operating normally.

Abstract: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a data unit with a high usage frequency is stored in a memory location with a low latency.

Abstract: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.

Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled.

Abstract: A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to logical addresses. The system evaluates the results of routine tests of memory and rearranges the physical addresses stored in the memory card ID register to provide an error-free portion at the desired logical address range. A separate memory configuration register stores a value representing the size of the memory cards. The value stored in the memory configuration register selects a subset of the logical memory address bits to obtain a logical card address. The logical card address selects a position in the memory card ID register to obtain the physical address of the memory card.

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) are providing in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.