Abstract: In a line termination unit integrated circuit in a point-to-multipoint network, a receiver receives an upstream transmission from a network termination unit within the point-to-multipoint network, a transmitter transmits a downstream transmission to a network termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the upstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the downstream transmission. The upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field, and the downstream transmission is a downstream transmission convergence frame format having an overhead field and a payload field.

Abstract: In a method for controlling timing of a transmission signal from a network termination device having a receiver and a transmitter, a signal is received at the receiver of the network termination device, the signal having been transmitted in accordance with a predetermined bit rate. A core clock signal for the receiver is determined based on the predetermined bit rate at which the signal was transmitted, and the core clock signal is communicated to the transmitter of the network termination device. At the transmitter of the network termination device, a phase adjusted clock signal is generated, and the phase adjusted clock signal is set as the transmitter clock signal. The transmitter clock signal is offset from the core clock signal, and the transmission signal is transmitted from the transmitter of the network termination device based on the transmitter clock signal.

Abstract: In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.

Abstract: In a network termination device integrated circuit in a point-to-multipoint network, a receiver receives a downstream transmission from a line termination unit within the point-to-multipoint network, a transmitter transmits an upstream transmission to the line termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the downstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the upstream transmission. The downstream transmission is an downstream transmission convergence frame format having an overhead field and a payload field, and the upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field.

Abstract: In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.

Abstract: In controlling data packet transmission for a passive optical network, a controller provides memory access and flow control of packet data from a host memory to an external optical network device, such as an optical line termination, optical network unit, or optical network termination. The controller is programmed to control packet data flow through the transmission buffer by resizing the transmission buffer to compensate for increases or decreases in bandwidth demand. For example, the transmission buffer may include a plurality of FIFOs, each of a different transmission container type and each capable of having a different bandwidth allocation, which allocation is changed by the controller in response any one of the FIFO's usage levels increasing above a high threshold or decreasing below a low threshold.

Abstract: In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.

Abstract: A method of synchronizing with a data transmission in a passive optical network, wherein the data transmission includes a plurality of data transmission frames each having i) a known transmission duration, and ii) a start boundary identified by a predetermined synchronization pattern. The method includes comparing a plurality of data patterns within the data transmission to at least part of a predetermined synchronization pattern; providing a comparison result for each comparison having a match between a data pattern and the at least part of the predetermined synchronization pattern; assigning a frame tracking signal to each one of the plurality of comparison results occurring within the known transmission duration; comparing one or more subsequent data patterns occurring in the data transmission to at least part of the predetermined synchronization pattern for each assigned frame tracking signal; and generating a synchronization signal associated with a selected one of the frame tracking signals.

Abstract: An apparatus including a first memory, a second memory, and a direct memory access engine. The first memory stores one or more packet descriptors. The second memory stores one or more packets for transmission via a communication link. The direct memory access engine is configured to i) determine when the one or more packet descriptors have been written, by a host, to the first memory, ii) read the one or more packet descriptors from the first memory in response to determining that the one or more packet descriptors have been written to the first memory by the host, iii) determine, using the one or more packet descriptors, one or more respective locations of one or more packets in a host memory, and iv) initiate a direct memory access transfer of the one or more packets from the one or more respective locations in the host memory to the second memory.

Abstract: In a method for controlling timing of an upstream from an optical network termination device to an optical line termination device, a downstream transmission is analyzed to determine a core clock rate for the termination device. The core clock signal is then used to determine a transmitter clock signal to be used for upstream transmission, where the transmitter clock signal is offset from the core clock signal. The offset transmitter clock signal may be determined in the receiver or in the transmitter of the termination device and by a delay lock loop or by a clock data recovery/generator circuitry. For example, the transmitter clock signal may be taken from a plurality of phase adjusted clock offset signals created by the clock data recovery/generator circuitry during identification of the core clock signal.

Abstract: In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer.

Abstract: In a method for recovering a data rate of an upstream transmission having rising edge transitions and falling edge transitions, an upstream transmission is coupled into a plurality of register banks, each register bank adapted to oversample the upstream transmission at a different phase offset of a clock signal. An edge transition state is determined for each of the register banks, each edge transition state corresponding to either a rising edge transition or a falling edge transition in the upstream transmission over a clock cycle. The edge transition states of the register banks are analyzed to determine a sampling point of the clock signal for sampling the upstream transmission. The upstream transmission may be transmitted through multiple data rate recovery circuits each operating at a different clock rate, for determining the optimal sampling point and the original data rate of the upstream transmission.

Abstract: A circuit and method to synchronize with a data transmission having a plurality of data transmission frames each with a start boundary identified by a predetermined synchronization pattern, includes comparing sets of data within the data transmission to a predetermined synchronization pattern. A frame tracking signal is assigned to each one of the plurality of comparison results that indicates a match between a data pattern within one of the plurality of sets of data and the predetermined synchronization pattern, including matches that occur multiple times within a known duration of the data transmission frame duration. Based on each frame tracking signal assigned to a comparison result, the start boundary of the data transmission frames is searched. The start boundary may be search by monitoring successive occurrences of the predetermined synchronization pattern in the data transmission at intervals of the known data transmission frame duration for each data matching data pattern.

Abstract: A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result.

Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.

Abstract: In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.

Abstract: In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer.

Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Abstract: A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding decisions. The switch buffers data frame header information in an internal memory for processing by the decision making logic. The switch employs a modular architecture that enables the decision making logic to perform its processing independently from other logic functions of the switch.