Abstract: A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.

Abstract: A network switch configured for switching data packets across multiple ports uses decision making device to generate frame forwarding information. The decision making device employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The decision making device also includes a memory to store frame headers to minimize the signaling between the decision making device and the receive devices.

Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.

Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

Abstract: A network switch configured for switching data packets across multiple ports and for supporting trunked data paths uses an address table to generate frame forwarding information. When a link in a trunked data path experiences a change in its operating status, the trunk data path is reconfigured to reflect the current operating conditions, without reprogramming the address table or powering down the switch.

Abstract: A system for accumulating data relating to performance parameters of a data communication system is provided in order to determine average values of these parameters. The system comprises multiple registers used for calculating average values of particular performance parameters, such as bus latency, interrupt latency, receive service routine time, and receive frame copy time. Each of the registers contains an event counter and a timer. The event counter increments upon occurrence of an event relating to the performance parameter accumulated by the corresponding register. The timer is activated by the occurrence of the event, and increments at a predetermined rate until the event comes to an end. The timer resumes incrementing when the next event occurs. As a result, the CPU is enabled to determine an average value of a particular parameter per an event relating to this parameter.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.

Abstract: A novel method of providing interleaved access to an address lookup table in a multiport communication system having a decision making engine for controlling data switching between receive and transmit ports. A source address (SA) lookup logic circuit and a destination address (DA) connected in a pipeline are enabled to alternately access the address table. An arbitration circuit provides the SA and DA logic circuits with automatic access to the address table in alternate time slots allocated to these logic circuits. Also, the arbitration circuit enables an aging circuit and a host processor to periodically access the address table in pre-selected time slots.

Abstract: A novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a prescribed algorithm. Then, a forwarding decision is made to determine the transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state. For example, pointers indicating memory locations for storing the corresponding received data packets may be transferred via the overflow bypass when the overflow state is detected.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generated frame forwarding information. The switch receives frame information including a source address and destination address along with a virtual local area network (VLAN) ID, if applicable. A decision-making engine searches a network address table to “learn” Medium Access Control (MAC) addresses without having to store receive port numbers by embedding the receive port number in the stored port vector fields.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port.

Abstract: A system is provided to support programming the size of a board-specific boot ROM in an embedded control system. Depending on functions performed by the embedded control system, a manufacturer decides which storage size of the boot ROM is required. An EEPROM of the embedded system is programmed to represent the selected boot ROM size. A network interface that provides data communications between the embedded control system and a data network has a boot ROM size detection circuit that supports boot ROM size programming. The boot ROM size detection circuit includes a ROM range register programmable from the EEPROM, and a boot ROM base address register programmable by an embedded controller via a PCI bus. During a power up process, the boot ROM size data from the EEPROM are loaded into the ROM range register. The embedded controller writes a predetermined value into the boot ROM base address register so as to read information representing the selected boot ROM size.

Abstract: A novel method of data processing in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. The receive ports include an expansion port for receiving data packets from another switching system, and a high-speed port for receiving data packets at a rate higher than data rates at regular receive ports. In accordance with the method of the present invention, data blocks representing received data packets are placed in a plurality of data queues corresponding to the plurality of the receive ports. The data queues are transferred in successive time slots to logic circuitry for determining at least one transmit port. The time slots assigned to each of the plurality of receive ports includes expansion port time slots assigned to the expansion port and high-speed time slots assigned to the high-speed port.

Abstract: An apparatus and a method ensure coherency between portions of data from a data generator which are sequentially read by a reading device at least one portion at a time, even though that data within the data generator is changing with time. The present invention stores a prior status of bits of data from the data generator at a prior time point. The present invention then transfers data portions from this stored data as the reading device continues to sequentially read portions of that stored data of the prior time point. When the reading device has finished reading the portions of the data of the prior time point, the present invention stores a subsequent status of bits of data from the data generator at a subsequent time point. Then, the process for ensuring coherency between portions of data, that are sequentially read, repeats for the subsequent time point.

Abstract: A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive.

Abstract: A register access controller prevents the occurrence of a live-lock condition when an electronic device specifies a register for access from a plurality of registers. The register access controller uses a partial spectrum address decoder instead of a full spectrum address decoder for decoding a register address specifying an implemented register to utilize the advantages of a smaller and simpler decoding circuitry and a faster response of a partial spectrum address decoder. The register access controller also monitors when the specified register address does not correspond to any of the implemented registers to provide a proper response to the electronic device in order to prevent a live-lock condition.

Abstract: Th present invention coordinates access to a shared resource, comprised of a plurality of segments, between a first device and a second device using an index and count mechanism. The present invention includes a respective descriptor, for each of the plurality of segments. Entries to the respective descriptors of the segments are maintained by the first device to inform the second device of activity between the first device and the shared resource. The present invention also includes a descriptor queue register, coupled to the first device and the second device. The first device writes an index into the descriptor queue register for indicating a starting descriptor of a corresponding segment that is available to the second device for access. The first device also writes a count into the descriptor queue register for indicating a subsequent number of descriptors, from the starting descriptor, of any corresponding segments that are available to the second device for access.

Abstract: A register access controller controls the timing of coupling a selected register of a plurality of register to a bus interface during a zero-wait continuous burst transfer of data from the plurality of registers to the bus interface. During the zero-wait continuous burst transfer of data, a newly selected register is coupled to the bus interface for each clock period. The register access controller of the present invention introduces a predetermined delay time between decoupling a previously selected register from the bus interface to coupling a newly selected register to the bus interface. In this manner, the register access controller prevents coupling of two registers to the bus interface at the same time thereby reducing the risk of integrated circuit damage that may result from simultaneous coupling of multiple registers to the bus interface.