Abstract: A buffer of a processing system allows younger stores to write to a data cache before an older store completes its write operation to the data cache while maintaining the appearance of committing stores in program order. To maintain the appearance that a blocked store completed its write operation to the data cache, the processing system cancels the blocked store while “locking” the cache line in the data cache in an exclusive state to which the blocked store is attempting to write. The data cache negatively acknowledges any probes to the cache line until the blocked store has completed the write operation. The buffer thus decouples completing the write operation from global observability of the write operation.

Abstract: A system for estimating power dissipation in an integrated circuit comprising a power converter and an amplifier, the system comprising processing circuitry configured to: receive a signal indicative of an output voltage to a load which, in use of the integrated circuit, is driven by the amplifier; receive a signal indicative of an output current to the load; determine an output power value based on the received signal indicative of the output voltage to the load and the received signal indicative of the output current to the load; receive a signal indicative of an input voltage to the power converter; receive a signal indicative of an average current input to the power converter; determine an input power value based on the received signal indicative of the input voltage to the power converter and the received signal indicative of the average current input to the power converter; and determine a power dissipation value based on the determined output power value and the determined input power value.

Abstract: The present disclosure relates generally to compositions of nitroglycerin and related organic nitrates, and methods for treating conditions such as Raynaud's phenomenon in which peripheral blood flow in a subject is compromised.

Abstract: The disclosed computer-implemented method for tracking miss requests using data cache tags can include generating a data cache miss request associated with data requested in connection with a cacheline and allocating a miss address buffer entry for the miss request. Additionally, the method can include, setting a fill-pending flag associated with the cacheline in response to the data associated with the data cache miss request being absent from a first data cache, and de-allocating the miss address buffer entry. In the event that another load or store operation requests the same data associated with the cacheline while the fill-pending flag is set, the method can include monitoring for a fill response associated with the miss request until the fill response is received. Upon receipt of the fill response, the method can include re-setting the fill-pending flag associated with the cacheline.

Abstract: A method for controlling an input current limit of boost converter circuitry, the method comprising: receiving a power dissipation value for the boost converter circuitry; and controlling an input current limit of the boost converter circuitry based on the power dissipation value.

Abstract: A connector for coiled tubing may include a main body configured for welding to a free end of the coiled tubing and having an internal stem extending distally therefrom. The stem may include a sleeve portion and the connector may include an alignment sleeve arranged on the sleeve portion of the stem and being free to rotate relative to the stem. The alignment sleeve may have a longitudinally extending groove on an outside surface thereof for receiving a longitudinal weld bead on an inside surface of the coiled tubing.

Abstract: Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.

Abstract: A friction reduction system disposable in a wellbore includes a first valve member including an inner surface which includes a valve seat; and a second valve member rotatable concentrically about a central axis of the first valve member and including a radial port coverable by the valve seat of the outer valve member, wherein the friction reduction system includes an open configuration that provides a maximum flow area through a valve of the friction reduction system including the second valve member and the first valve member, wherein the friction reduction system includes a closed configuration that provides a minimum flow area through the valve which is less than the maximum flow area, and wherein the friction reduction system is configured to generate a pressure pulse in a fluid flowing through the friction reduction system in response to the friction reduction system transitioning from the open configuration to the closed configuration.

Abstract: A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.

Abstract: An apparatus includes a plurality of load buses and a load store unit that includes a plurality of load ports to access the plurality of load buses. The load store unit performs a gather operation to concurrently gather a plurality of subsets of data from a memory via the plurality of load buses in a first mode. The apparatus also includes a register that is partitioned into a plurality of portions to hold the plurality of subsets of data provided by the load store unit. The load store unit ignores exceptions or faults while performing the gather operation in the first mode and transitions to a second mode in response to an exception or fault. Two lanes are dispatched to concurrently perform the gather operation per clock cycle in the first mode and a single lane is dispatched to perform the gather operation per clock cycle in the second mode.

Abstract: A system and method for load fusion fuses small load operations into fewer, larger load operations. The system detects that a pair of adjacent operations are consecutive load operations, where the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive load micro-operations refers to both of the adjacent micro-operations being load micro-operations. The consecutive load operations are then reviewed to determine if the data sizes are the same and if the load operation addresses are consecutive. The two load operations are then fused together to form one load micro-operation with twice the data size and one load data micro-operation with no load component.

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

Abstract: A friction reduction system disposable in a wellbore includes a first valve member including an inner surface which includes a valve seat; and a second valve member rotatable concentrically about a central axis of the first valve member and including a radial port coverable by the valve seat of the outer valve member, wherein the friction reduction system includes an open configuration that provides a maximum flow area through a valve of the friction reduction system including the second valve member and the first valve member, wherein the friction reduction system includes a closed configuration that provides a minimum flow area through the valve which is less than the maximum flow area, and wherein the friction reduction system is configured to generate a pressure pulse in a fluid flowing through the friction reduction system in response to the friction reduction system transitioning from the open configuration to the closed configuration.

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

Abstract: A system and method for a lightweight fence is described. In particular, micro-operations including a fencing micro-operation are dispatched to a load queue. The fencing micro-operation allows micro-operations younger than the fencing micro-operation to execute, where the micro-operations are related to a type of fencing micro-operation. The fencing micro-operation is executed if the fencing micro-operation is the oldest memory access micro-operation, where the oldest memory access micro-operation is related to the type of fencing micro-operation. The fencing micro-operation determines whether micro-operations younger than the fencing micro-operation have load ordering violations and if load ordering violations are detected, the fencing micro-operation signals the retire queue that instructions younger than the fencing micro-operation should be flushed. The instructions to be flushed should include all micro-operations with load ordering violations.

Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

Abstract: Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.

Abstract: A system and method for load queue (LDQ) and store queue (STQ) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing LDQ and STQ entries are delayed until address generation time. This allows the load and store operations to dispatch, and younger operations (which may not be store and load operations) to also dispatch and execute their instructions. The address generation of the load or store operation is held at an address generation scheduler queue (AGSQ) until a load or store queue entry is available for the operation. The tracking of load queue entries or store queue entries is effectively being done in the AGSQ instead of at the decode engine. The LDQ and STQ depth is not visible from a decode engine's perspective, and increases the effective processing and queue depth.

Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.