Abstract: The present invention provides a method and apparatus for checkpointing registers for transactional memory. Some embodiments of the apparatus include first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers. The mapping is responsive to a transaction modifying one or more of the first values associated with the architectural registers. Some embodiments of the apparatus also include microcode configured to write contents of the first physical registers to a memory in response to the transaction modifying first values associated with a number of the architectural registers that is larger than the predetermined number.

Abstract: A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.

Abstract: A method and apparatus use one or more inclusion bits and a victim bit to filter probes to shared caches. One embodiment of the method includes filtering a probe or snoop of one or more of a plurality of first caches based on a plurality of first bits, such as inclusion bits, associated with a line indicated by the probe or snoop. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit, such as a victim probe bit, indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. The first caches may be L1 caches and the first bits may be stored in an L2 cache of a multilevel cache.

Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

Abstract: The present invention provides a method and apparatus for checkpointing registers for transactional memory. Some embodiments of the apparatus include first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers. The mapping is responsive to a transaction modifying one or more of the first values associated with the architectural registers. Some embodiments of the apparatus also include microcode configured to write contents of the first physical registers to a memory in response to the transaction modifying first values associated with a number of the architectural registers that is larger than the predetermined number.

Abstract: A method and apparatus for tracking and reclaiming physical registers is presented. Some embodiments of the apparatus include rename logic configurable to map architectural registers to physical registers. The rename logic is configurable to bypass allocation of a physical register to an architectural register when information to be written to the architectural register satisfies a bypass condition. Some embodiments of the apparatus also include a plurality of first bits associated with the architectural registers. The rename logic is configurable to set one of the first bits to indicate that allocation of a physical register to the corresponding architectural register has been bypassed.

Abstract: A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.

Abstract: The claimed subject matter provides a method and apparatus for filtering probes to shared caches. One embodiment of the method includes filtering a probe of one or more of a plurality of first caches based on a plurality of first bits associated with a line indicated by the probe. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches.

Abstract: The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from a register to an execution stage in a pipeline along a first data path that includes a lane crossing stage configured to change a first mapping of the register to the execution stage to a second mapping. The method also includes concurrently conveying the bits along a second data path from the register to the execution stage that bypasses the lane crossing stage. The method further includes selecting the first or second data path to provide the bits to the execution stage.

Abstract: The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from a register to an execution stage in a pipeline along a first data path that includes a lane crossing stage configured to change a first mapping of the register to the execution stage to a second mapping. The method also includes concurrently conveying the bits along a second data path from the register to the execution stage that bypasses the lane crossing stage. The method further includes selecting the first or second data path to provide the bits to the execution stage.

Abstract: A method for generating predictions of rocket motor ballistic performance at specific firing temperatures and for generating data profiles for analysis. The method requires generally available specifications for the rocket motor to be tested and test data from one or more test firings at a known temperature. The method is implemented in software form and generates pressure and thrust versus time data at a selected temperature. The method generates a burnback profile with a correct final web that integrates to the correct final propellant weight as well as a throat area profile and thrust coefficient profile, for the test firing temperature and for the temperature to be predicted.

Abstract: A junction box assembly for a vehicle having a junction box, a positive conductive terminal, a bus bar and a conductive jump-start terminal that are coupled to a battery cable in a manner wherein high-current electrical energy does not flow though the junction box during a jump-start event. The jump-start terminal is configured with a blade portion that provides the user of the vehicle with a convenient point to which the positive lead of a jumper cable may be attached during jump-starting operations.

Abstract: The apparatus consists of a cylindrical combustion chamber supported on the top end of a cylindrical shock tube. The lower end of the shock tube is held a distance from the ground on which the apparatus is used inside a conical enclosure. The conical enclosure is attached to a circular base with a circular hole at its center. The interior of the conical enclosure is covered by a layer of acoustical insulation. The diameter of the shock tube is less than the diameter of the combustion chamber. The cone angle of the conical enclosure is about 50.degree..

Abstract: An antioxidant additive combination for lubricating oils is prepared by combining (a) a sulfur containing molybdenum compound prepared by reacting an ammonium tetrathiomolybdate, and a basic nitrogen compound, with (b) an organic sulfur compound.

Abstract: An antioxidant additive combination for lubricating oils is prepared by combining (a) a sulfur containing molybdenum compound prepared by reacting an acidic molybdenum compound, a basic nitrogen compound, and carbon disulfide, with (b) an organic sulfur compound.

Abstract: An antioxidant additive combination for lubricating oils is prepared by combining (a) a sulfur containing molybdenum compound prepared by reacting an acidic molybdenum compound, a basic nitrogen compound, and carbon disulfide, with (b) an aromatic amine compound.

Abstract: An antioxidant additive combination for lubricating oils is prepared by combining (a) a sulfur containing molybdenum compound prepared by reacting an acidic molybdenum compound, a basic nitrogen compound, and a sulfur compound, with (b) an aromatic amine compound.

Abstract: An antioxidant additive combination for lubricating oils is prepared by combining (a) a sulfur containing molybdenum compound prepared by reacting an acidic molybdenum compound, a basic nitrogen compound, and a sulfur compound, with (b) an organic sulfur compound.

Abstract: A solar heated portable structure comprising a flexible bottom panel, a flexible side assembly and a flexible transmitting panel, all coupled together and supported to form an enclosed chamber. The transmitting panel is capable of transmitting a majority of the radiant energy from the solar radiation spectrum to heat the enclosed chamber like a sauna and has an area at least 0.7 the area of the bottom panel to maximize heating while minimizing material costs. The transmitting panel can be transparent to ultraviolet radiation to allow persons inside the chamber to be tanned.

Abstract: Antioxidant additives for lubricating oil are prepared by (1) combining a polar solvent, an acidic molybdenum compound and an oil-soluble basic nitrogen compound to form molybdenum-containing complex and (2) contacting said complex with carbon disulfide to form a sulfur-and molybdenum-containing composition.