Abstract: A vehicular exterior rearview mirror assembly includes a mounting arm and a mirror head at one end of the mounting arm distal from an attachment portion of the mounting arm that is configured for attachment at a vehicle. A mirror reflective element is fixedly attached at the mirror head. An innermost side of the mirror reflective element is attached at a front side of an attachment plate. The mirror reflective element moves in tandem with movement of the mirror head relative to the mounting arm when the driver of the vehicle operates an electrically-operable actuator. The attachment plate includes wall structure that extends from the front side of the attachment plate and circumscribes and spans the perimeter circumferential edge of the glass substrate and does not encroach onto and does not overlap the front surface of the glass substrate of the exterior mirror reflective element.

Abstract: A honeycomb structure (110) includes intersecting porous walls (106). Inlet channels (108i) and outlet channels (108o) are formed by the intersecting porous walls (106), wherein the inlet channels (108i) comprise inlet hydraulic diameters (HDi) and the outlet channels (108o) comprise outlet hydraulic diameters (HDo). The inlet channels (108i) comprise inlet corners (220i) with inlet corner radii (Ri) and the outlet channels (108o) comprise outlet corners (2200) with outlet corner radii (Ro). A centerpost (124) is defined by adjacent opposing inlet corners (220i) of two of the inlet channels (108i) and adjacent opposing outlet corners (2200) of two of the outlet channels (108o). A first diagonal length (D1) is a shortest distance between the opposing outlet corners (220o) of the two outlet channels (108o) and a second diagonal length (D2) is a shortest distance between the opposing inlet corners (220i) of the two inlet channels (108i).

Abstract: Disclosed herein is a permanent magnet comprising: a plurality of aligned iron nitride nanoparticles wherein the iron nitride nanoparticles include ??-Fe16N2 phase domains; wherein a ratio of integrated intensities of an ??-Fe16N2 (004) x-ray diffraction peak to an ??-??-Fe16N2 (202) x-ray diffraction peak for the aligned iron nitride nanoparticles is greater than at least 7%, wherein the diffraction vector is parallel to alignment direction, and wherein the iron nitride nanoparticles exhibit a squareness measured parallel to the alignment direction that is greater than a squareness measured perpendicular to the alignment direction.

Abstract: Disclosed herein is a permanent magnet comprising: a plurality of aligned iron nitride nanoparticles wherein the iron nitride nanoparticles include ??-Fe16N2 phase domains; wherein a ratio of integrated intensities of an ??-Fe16N2 (004) x-ray diffraction peak to an ??-??-Fe16N2 (202) x-ray diffraction peak for the aligned iron nitride nanoparticles is greater than at least 7%, wherein the diffraction vector is parallel to alignment direction, and wherein the iron nitride nanoparticles exhibit a squareness measured parallel to the alignment direction that is greater than a squareness measured perpendicular to the alignment direction.

Abstract: A honeycomb structure (110) includes intersecting porous walls (106). Inlet channels (108i) and outlet channels (108o) are formed by the intersecting porous walls (106), wherein the inlet channels (108i) comprise inlet hydraulic diameters (HDi) and the outlet channels (108o) comprise outlet hydraulic diameters (HDo). The inlet channels (108i) comprise inlet corners (220i) with inlet corner radii (Ri) and the outlet channels (108o) comprise outlet corners (2200) with outlet corner radii (Ro). A centerpost (124) is defined by adjacent opposing inlet corners (220i) of two of the inlet channels (108i) and adjacent opposing outlet corners (2200) of two of the outlet channels (108o). A first diagonal length (D1) is a shortest distance between the opposing outlet corners (220o) of the two outlet channels (108o) and a second diagonal length (D2) is a shortest distance between the opposing inlet corners (220i) of the two inlet channels (108i).

Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Abstract: A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a new distribution of mobile charge carriers in the bulk region of the semiconductor substrate, which improves device and circuit performance by lowering gate capacitance, improving effective carrier mobility ?, reducing noise, reducing gate insulator leakage, reducing hot carrier effect and improving reliability.

Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a channel region. The improvements from the controllability of the placement of the Schottky-barrier junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.