Abstract: A microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.