Abstract: A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET and a p channel, analog VeSFET. The method may further comprise forming, on the SOI wafer, at least one of a JFET, a BJT and a LT-MOM capacitor. The method may further comprise forming the n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET, and a p channel, analog VeSFET, according to a periodic design based on a unit circle. The method may comprise modifying a design of the semiconductor node, according to a three-dimensional architecture, to form a modified semiconductor node, and fabricating the modified semiconductor node on substrate, along with at least one other node of a different node type.

Abstract: A non-volatile memory device (VeSFlash) comprises a vertical slit field effect transistor (VeSFET) device comprising a semiconductor portion defining a source end, a drain end, and a slit portion between the source end and the drain end. The VeSFlash non-volatile memory device further comprises at least one floating gate coupled to a side of the slit portion through an insulating layer. The floating gate is coupled to a contact through a second insulating layer. The VeSFlash non-volatile memory device further comprises either another floating gate or an independent control gate. In the case of comprising a control gate coupled to a side wall of the slit portion through a third insulating layer, and the control gate further coupled to a second contact, it is configured to accommodate an access signal, and the floating gate configured to accommodate a data signal.

Abstract: Systems and methods are presented for power supply noise cancellation in a microphone package. A first node on a MEMS microphone package is coupled to an inverted voltage signal of a power supply output. A summing node is connected to both the first node and a second node. The second node is coupled to a non-inverted voltage signal of the power supply output. Because the parasitic capacitance of the MEMS microphone package is substantially equivalent relative to both the first node and the second node, the summing node outputs a noise-reduced summed voltage signal. An adjustable trim module is coupled to the first node and configured to adjust a reduction of a power supply noise in the summed voltage signal from the summing node.

Abstract: Systems and methods for preventing electrical leakage in a MEMS microphone. In one embodiment, the MEMS microphone includes a semiconductor substrate, an electrode, a first insulation layer, and a doped region. The first insulation layer is formed between the electrode and the semiconductor substrate. The doped region is implanted in at least a portion of the semiconductor substrate where the semiconductor substrate is in contact with the first insulation layer. The doped region is also electrically coupled to the electrode.

Abstract: A MEMS capacitive sensor biasing circuit. The circuit includes a high-voltage (HV) NMOS switch, an inductor, a diode, and a capacitor. The HV NMOS switch has a source coupled to ground. The inductor has a first node coupled to a drain of the HV NMOS switch, and a second node coupled to a DC power source supplying a first DC voltage. The diode has an anode coupled to the first node of the inductor and the drain of the HV NMOS switch. The capacitor has a first node coupled to a cathode of the diode, and a second node coupled to the ground.

Abstract: Systems and methods for preventing electrical leakage in a MEMS microphone. In one embodiment, the MEMS microphone includes a semiconductor substrate, an electrode, a first insulation layer, and a doped region. The first insulation layer is formed between the electrode and the semiconductor substrate. The doped region is implanted in at least a portion of the semiconductor substrate where the semiconductor substrate is in contact with the first insulation layer.

Abstract: Systems and methods are presented for power supply noise cancellation in a microphone package. A first node on a MEMS microphone package is coupled to an inverted voltage signal of a power supply output. A summing node is connected to both the first node and a second node. The second node is coupled to a non-inverted voltage signal of the power supply output. Because the parasitic capacitance of the MEMS microphone package is substantially equivalent relative to both the first node and the second node, the summing node outputs a noise-reduced summed voltage signal. An adjustable trim module is coupled to the first node and configured to adjust a reduction of a power supply noise in the summed voltage signal from the summing node.

Abstract: A MEMS microphone package is described that includes a first node and a second node having nearly equivalent 3D parasitic capacitances relative to a preamplifier of the microphone package, such that any noise generated on the first node is equivalent to any noise generated on the second node. An external power supply is connected to the first node and provides a bias voltage signal to the MEMS microphone package via the first node. An inverting amplifier is connected between the power supply and the second node. A third node is connected to the first node through a packaging parasitic capacitor, while the second node is connected to the third node through either an intended parasitic capacitor or an explicit capacitor. The noise coupled from the external power supply to the third node is then cancelled by summing the inverted power supply noise into the third node.

Abstract: An adjustable charge pump system. The system includes a voltage regulator, a clock circuit, a voltage adjustment circuit, and a charge pump. The voltage regulator is configured to receive an input voltage and output a regulated voltage. The clock circuit is coupled to the voltage regulator and receives the regulated voltage. The voltage adjustment circuit is coupled to the voltage regulator and is configured to receive the regulated voltage and to output a driver voltage. The charge pump includes a plurality of stages. The output of the adjustable charge pump system is adjusted by disabling one or more stages of the first stage and the plurality of subsequent stages.

Abstract: A MEMS microphone package is described that includes a first node and a second node having nearly equivalent 3D parasitic capacitances relative to a preamplifier of the microphone package, such that any noise generated on the first node is equivalent to any noise generated on the second node. An external power supply is connected to the first node and provides a bias voltage signal to the MEMS microphone package via the first node. An inverting amplifier is connected between the power supply and the second node. A third node is connected to the first node through a packaging parasitic capacitor, while the second node is connected to the third node through either an intended parasitic capacitor or an explicit capacitor. The noise coupled from the external power supply to the third node is then cancelled by summing the inverted power supply noise into the third node.

Abstract: Charge pump capacitor assemblies and methods of manufacturing the same. One charge pump capacitor assembly includes a charge pump capacitor and a silicon substrate. The charge pump capacitor includes: a silicon-based charge pump capacitor oxide layer, a first terminal on a first side of the silicon-based charge pump layer, a second terminal on a second side of the silicon-based charge pump capacitor oxide layer opposite the first side, and a field oxide layer mounted adjacent the second terminal. The charge pump capacitor is coupled to the silicon substrate. The silicon substrate is etched to reduce contact between the silicon substrate and the field oxide layer.

Abstract: A micro-speaker. The micro-speaker includes a first plate, a second plate, and a diaphragm. The first plate is biased to a first voltage. The second plate is biased to a second voltage. The diaphragm is positioned between the first plate and the second plate and is configured to receive a digital signal. The digital signal causes the diaphragm to cycle between fully displaced toward the first plate and fully displaced toward the second plate, creating air pressure pulses that mimic the digital signal.

Abstract: Charge pump capacitor assemblies and methods of manufacturing the same. One charge pump capacitor assembly includes a charge pump capacitor and a silicon substrate. The charge pump capacitor includes: a silicon-based charge pump capacitor oxide layer, a first terminal on a first side of the silicon-based charge pump layer, a second terminal on a second side of the silicon-based charge pump capacitor oxide layer opposite the first side, and a field oxide layer mounted adjacent the second terminal. The charge pump capacitor is coupled to the silicon substrate. The silicon substrate is etched to reduce contact between the silicon substrate and the field oxide layer.

Abstract: An adjustable charge pump system. The system includes a voltage regulator, a clock circuit, a voltage adjustment circuit, and a charge pump. The voltage regulator is configured to receive an input voltage and output a regulated voltage. The clock circuit is coupled to the voltage regulator and receives the regulated voltage. The voltage adjustment circuit is coupled to the voltage regulator and is configured to receive the regulated voltage and to output a driver voltage. The charge pump includes a plurality of stages. The output of the adjustable charge pump system is adjusted by disabling one or more stages of the first stage and the plurality of subsequent stages.

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

Abstract: A high-voltage MEMS biasing network. The network has a reset mode wherein a capacitive sensor is charged, and a functional mode wherein the MEMS biasing network provides a high impedance between the capacitive sensor and a bias voltage source. The network includes a biasing circuit, a mirror circuit, and a control circuit. The biasing circuit and the mirror circuit have a charging state and a high impedance state. The control circuit includes a first branch that controls the biasing circuit and a second branch that controls the mirror circuit. The biasing network receives a logic control signal, the first branch puts the biasing circuit into the charging state when the logic control signal is a first logic signal, and puts the biasing circuit into the high impedance state when the logic control signal is a second logic signal.

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

Abstract: A micro-speaker. The micro-speaker includes a first plate, a second plate, and a diaphragm. The first plate is biased to a first voltage. The second plate is biased to a second voltage. The diaphragm is positioned between the first plate and the second plate and is configured to receive a digital signal. The digital signal causes the diaphragm to cycle between fully displaced toward the first plate and fully displaced toward the second plate, creating air pressure pulses that mimic the digital signal.

Abstract: A self-tuning MEMS microphone. The microphone includes a capacitive sensor, an amplifier, a signal converter, a frequency generator, a micro-speaker, and a controller. The capacitive sensor is configured to detected a sound wave and output an electric signal based on the sound wave. The amplifier is coupled to the capacitive sensor, and configured to amplify the electric signal. The signal converter is coupled to the amplifier, and configured to adjust a frequency response of the amplified electric signal. The frequency generator is configured to output an AC electric signal. The micro-speaker is coupled to the frequency generator, and configured to convert the AC electric signal into a sound wave. The controller is coupled to the signal converter and the frequency generator. The controller is configured to direct the frequency generator to output the AC electric signal at a predetermined frequency and to detect an amplified electric signal generated by the capacitive sensor based on the AC electric signal.

Abstract: A MEMS capacitive sensor biasing circuit. The circuit includes a high-voltage (HV) NMOS switch, an inductor, a diode, and a capacitor. The HV NMOS switch has a source coupled to ground. The inductor has a first node coupled to a drain of the HV NMOS switch, and a second node coupled to a DC power source supplying a first DC voltage. The diode has an anode coupled to the first node of the inductor and the drain of the HV NMOS switch. The capacitor has a first node coupled to a cathode of the diode, and a second node coupled to the ground.