Abstract: A high-voltage MEMS biasing network. The network has a reset mode wherein a capacitive sensor is charged, and a functional mode wherein the MEMS biasing network provides a high impedance between the capacitive sensor and a bias voltage source. The network includes a biasing circuit, a mirror circuit, and a control circuit. The biasing circuit and the mirror circuit have a charging state and a high impedance state. The control circuit includes a first branch that controls the biasing circuit and a second branch that controls the mirror circuit. The biasing network receives a logic control signal, the first branch puts the biasing circuit into the charging state when the logic control signal is a first logic signal, and puts the biasing circuit into the high impedance state when the logic control signal is a second logic signal.

Abstract: A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the outputs of the main differential amplifier 30 through feedback paths. The output signals from the correction amplifier 20 are combined with the inputs to the main amplifier 30 such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the outputs of the main differential amplifier 30 through feedback paths. The output signals from the correction amplifier 20 are combined with the inputs to the main amplifier 30 such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: A microphone bias current detection circuit includes: a microphone circuit 18; an amplifier 10 having a first output and a second output, the first output is coupled to the microphone circuit 18 for providing a bias current to the microphone circuit 18, the second output provides a sampled current Is proportional to the bias current; a first switch 30 having a first end coupled to the second output of the amplifier 10; a resistor 38 having a first end coupled to a second end of the first switch 30; and a second switch 32 coupled between the first end of the resistor 38 and a reference current source.

Abstract: A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control circuit (106) and a output stage bias reference circuit (108). The input gain stage (102) includes differential inputs (IN−, IN+) and differential outputs (A1, B1). The output stage (104), having control transistors, connects to each differential output (A1, B1) of the input stage (102). and a quiescent current control circuit (106) deriving common mode feedback control signal (VCS1) from the differential outputs (A1, B1) and voltage bias node (D1). A quiescent current control circuit (106) derives the common mode feedback control signal (VCS1) to maintain the voltage of the input gain stage transistors (M3, M4) at a desired level.

Abstract: A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control circuit (106) and a output stage bias reference circuit (108). The input gain stage (102) includes differential inputs (IN−, IN+) and differential outputs (A1, B1). The output stage (104), having control transistors, connects to each differential output (A1, B1) of the input stage (102). and a quiescent current control circuit (106) deriving common mode feedback control signal (VCS1) from the differential outputs (A1, B1) and voltage bias node (D1). A quiescent current control circuit (106) derives the common mode feedback control signal (VCS1) to maintain the voltage of the input gain stage transistors (M3, M4) at a desired level.

Abstract: The two-stage power amplifier includes: a first stage transconductor 60; and a second stage having at least two parallel output branches 57-59 supplying current to an output node 89, each output branch has an input coupled to an output of the first stage transconductor 60.

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A microphone bias amplifier circuit (30) and method for biasing a microphone with an amplifier circuit. The amplifier circuit (30) has an input stage (34) coupled to an output stage (40). The output stage (40) includes a first transistor (M1) coupled to a feedback loop (32) provides a variable source current (13) to the first transistor (M1) and the output stage output Vout. The feedback loop (32) includes an amplifier (36) coupled to the first transistor (M1) and a first current source (I2) conducted through a second transistor (M2) and coupled to the amplifier (36). The amplifier (36) controllably drives a third transistor (M3) coupled to a voltage source (AVDD) to generate the variable current source (I2). The gates of the first (M1) and second (M2) transistors are coupled together and driven by the input stage (34).

Abstract: The distortion correction circuit includes: a main amplifier 30 having a first resistor 36 coupled from an output of the main amplifier 30 to a first input of the main amplifier 30, and a second resistor 34 coupled between the first input of the main amplifier 30 and a first input signal node; a correction loop amplifier 32 having an output coupled to a second input of the main amplifier 30, an output of the main amplifier 30 coupled to a first input of the correction loop amplifier 32, a second input of the correction loop amplifier 32 coupled to a second input signal node.

Abstract: A low noise, low current, high bandwidth differential amplifier circuit (30), including a first amplifier (44) driving a first transistor X1 and having a first current source I2 coupled to an input of the first amplifier (44). A first feedback resistor R3 is coupled between the first current source I2 and the first transistor X1, and a second resistor R4 is coupled to the first resistor R3. A second amplifier (46) drives a second transistor X2, and has a second current source I3 coupled to an input of the second amplifier 46. A third feedback resistor R5 is coupled between the second current source I3 and the second transistor X2. A fourth resistor R6 is coupled to the third resistor R5. The first R3 and third R5 feedback resistors are driven by the first I2 and second I3 current sources rather than by the first (44) and second (46) amplifiers, respectively, allowing the first and second amplifiers (44, 46) to be single stage amplifiers.

Abstract: An ultra low voltage CMOS, class AB power amplifier has internal compensation using only parasitic gate capacitance.

Abstract: An analog clipping circuit includes: a main amplifier 20; a feedback resistor 26 coupled between a first input of the main amplifier 20 and an output of the main amplifier 20; a first current source 50 coupled in parallel with the feedback resistor 26; a first clipping amplifier 42 coupled to the first current source 50 for controlling the first current source 50, the first clipping amplifier 42 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a first reference node; a second current source 54 coupled in parallel with the feedback resistor 26; and a second clipping amplifier 44 coupled to the second current source 54 for controlling the second current source 54, the second clipping amplifier 44 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a reference node.