Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.

Abstract: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

Abstract: A variable reluctance sensor system for processing a variable reluctance sensor signal including an arming comparator and an arming circuit. The arming comparator compares the variable reluctance sensor signal with an arming threshold which decreases proportional to 1/t from a predetermined maximum level and asserts an armed signal when the variable reluctance sensor signal reaches the arming threshold. The arming threshold may be decreased based on a scaling factor multiplied by 1/t to ensure detection of each pulse of the variable reluctance sensor signal. The arming threshold may decrease to a predetermined minimum level sufficiently low to intersect the variable reluctance sensor signal and sufficiently high relative to an expected noise level. The arming threshold is reset in response to a timing event, such as zero crossing of the variable reluctance sensor signal.

Abstract: A circuit including a carrier amplifier having an input, an output, a first transistor coupled to a first power supply voltage terminal for receiving a modulated power supply voltage, and a second transistor coupled to a second power supply voltage terminal for receiving a fixed power supply voltage is provided. The circuit further includes a peaking amplifier having an input coupled to the input of the carrier amplifier and an output coupled to the output of the carrier amplifier.

Abstract: A method of operating a battery system includes a plurality of battery cells coupled in series. The plurality of cells includes at least three battery cells coupled in series. The method includes determining a cell with the greatest charge excess of the plurality of battery cells. The method further includes determining a cell with the greatest charge deficit of the plurality of battery cells. The method further includes discharging the cell with the greatest charge excess to charge, with a voltage converter, the cell with the greatest charge deficit.

Abstract: A DC to DC converter has first and second transistor coupled at a first node and coupled between first and second power supply terminals. An inductor has a first terminal coupled to the first node and a second terminal coupled to an output terminal for receiving a variable load. Transistor drive circuitry controls conduction of the first and second transistor in a non-overlapping conduction operation. A duty cycle controller controls a duty cycle for the first transistor and the second transistor. Control circuitry determines a mode of operation by monitoring cycles of operation and detecting a predetermined pattern of cycles in which inductor current becomes negative. A first mode of operation permits both the first transistor and the second transistor to alternately conduct and a second mode of operation does not permit the second transistor to conduct during each cycle when the inductor current is reduced to substantially zero.

Abstract: A method of operating a battery system includes a plurality of battery cells coupled in series. The plurality of cells includes at least three battery cells coupled in series. The method includes determining a cell with the greatest charge excess of the plurality of battery cells. The method further includes determining a cell with the greatest charge deficit of the plurality of battery cells. The method further includes discharging the cell with the greatest charge excess to charge, with a voltage converter, the cell with the greatest charge deficit.

Abstract: A switching regulator includes a capacitor, a charge control circuit, a discharge detector, a switch circuit, and a feedback circuit. The charge control circuit charges and discharges the capacitor. The discharge detector has an input coupled to the capacitor to detect when the capacitor has discharged to a predetermined level to indicate an over-current condition. The switch circuit is coupled to receive an input voltage. The switch circuit is made conductive and non conductive by a switching signal for supplying an output voltage at a regulated voltage level. The duty cycle of the switching signal is reduced in response to an indication of an over-current condition. The feedback circuit is for controlling a discharge rate of the capacitor.

Abstract: An electrostatic occupant detection system includes an electrostatic sensor and an electronic control unit. The electronic control unit is switchable between an occupant determination state in which the electronic control unit outputs a sine wave having a constant amplitude and a diagnosis state in which the electronic control unit maintains a voltage of the electrostatic sensor at a constant level. The electronic control unit gradually changes at least one of an amplitude and a frequency of the sine wave either when the electronic control unit switches from the occupant determination state to the diagnosis state and/or when the electronic control unit switches from the diagnosis state to the occupant determination state.

Abstract: A circuit comprises a delta phi generator, a startup circuit, and a level detector. The delta phi generator has a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state. The startup circuit is coupled to the delta phi generator. The startup circuit ensures that the delta phi generator does not operate in the undesirable operating state. The level detector comprises a comparator with an offset. The comparator has a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit. The level detector detects the delta phi voltage, and in response, disables the startup circuit.

Abstract: In a D.C. to D.C. converter, an input voltage is received via an inductor at an input terminal and stored onto a capacitor of an integrator. A first switch is coupled between the input terminal and a reference terminal such as ground and thereby fluxes the inductor. The input voltage stored on the capacitor falls at a rate determined by the integrator circuit and an initial value of the input voltage. After a time duration, the first switch becomes nonconductive. Current flows from the inductor through a diode to an output terminal until a second switch across the diode is made conductive. Stored voltage on the capacitor of the integrator increases in response to the second switch being conductive. The stored voltage on the capacitor is continuously compared with a reference voltage. The second switch is made nonconductive when the stored voltage on the capacitor exceeds the reference voltage.

Abstract: In a D.C. to D.C. converter, an input voltage is received via an inductor at an input terminal and stored onto a capacitor of an integrator. A first switch is coupled between the input terminal and a reference terminal such as ground and thereby fluxes the inductor. The input voltage stored on the capacitor falls at a rate determined by the integrator circuit and an initial value of the input voltage. After a time duration, the first switch becomes nonconductive. Current flows from the inductor through a diode to an output terminal until a second switch across the diode is made conductive. Stored voltage on the capacitor of the integrator increases in response to the second switch being conductive. The stored voltage on the capacitor is continuously compared with a reference voltage. The second switch is made nonconductive when the stored voltage on the capacitor exceeds the reference voltage.

Abstract: A DC to DC converter has first and second transistor coupled at a first node and coupled between first and second power supply terminals. An inductor has a first terminal coupled to the first node and a second terminal coupled to an output terminal for receiving a variable load. Transistor drive circuitry controls conduction of the first and second transistor in a non-overlapping conduction operation. A duty cycle controller controls a duty cycle for the first transistor and the second transistor. Control circuitry determines a mode of operation by monitoring cycles of operation and detecting a predetermined pattern of cycles in which inductor current becomes negative. A first mode of operation permits both the first transistor and the second transistor to alternately conduct and a second mode of operation does not permit the second transistor to conduct during each cycle when the inductor current is reduced to substantially zero.

Abstract: A circuit comprises a delta phi generator, a startup circuit, and a level detector. The delta phi generator has a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state. The startup circuit is coupled to the delta phi generator. The startup circuit ensures that the delta phi generator does not operate in the undesirable operating state. The level detector comprises a comparator with an offset. The comparator has a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit. The level detector detects the delta phi voltage, and in response, disables the startup circuit.

Abstract: A circuit including a carrier amplifier having an input, an output, a first transistor coupled to a first power supply voltage terminal for receiving a modulated power supply voltage, and a second transistor coupled to a second power supply voltage terminal for receiving a fixed power supply voltage is provided. The circuit further includes a peaking amplifier having an input coupled to the input of the carrier amplifier and an output coupled to the output of the carrier amplifier.

Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).

Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.

Abstract: A dual loop DC-to-DC converter is provided that includes a first control loop that maintains a DC output voltage (VOUT) less than or equal to a desired maximum value of the VOUT, a second control loop that operates simultaneously with the first control loop and maintains a DC input voltage (VIN) greater than or equal to a desired minimum value of the VIN, and a duty cycle selection module. The first control loop generates a first clock signal having a first duty cycle, and the second control loop generates a second clock signal having a second duty cycle. The duty cycle selection module continuously determines which one of the first duty cycle and the second duty cycle has a lower duty cycle value, and continuously generates a PWM output signal having a modulated duty cycle equal to the lower duty cycle value.

Abstract: A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

Abstract: A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.