Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.

Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall.

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.

Abstract: A three-dimensional (3-D) integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of non-contiguous dummy walls patterned in a corresponding dielectric level around a circuit wire keep out zone (KOZ). The non-contiguous dummy walls are formed in the circuit wire KOZ and have an outer side and an opposing inner side that extend along a first direction to define a length. A circuit wire segment is located at a first metal level and a second circuit wire segment is located at a second metal level different from the first metal level. The first and second metal levels are located adjacent the inner side of at least one non-contiguous dummy wall.

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract: A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Abstract: An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.