Abstract: The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming.

Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

Abstract: The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

Abstract: A method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. The fuse link has a nominal maximum programming current and corresponding combinations of a programming voltage and a gate voltage associated with the nominal maximum programming current. A first programming current pulse is generated to provide a programming current less than the maximum programming current. The first programming current pulse causes electromigration to increase the resistance of the fuse link. A subsequent programming current pulse is applied using a combination of gate voltage and programming voltages which if applied to the fuse link absent any electromigration would result in a programming current greater than the nominal maximum programming current. However, the resistance created by the first programming pulse reduces the programming current of the subsequent programming pulse to a level below the maximum programming current.

Abstract: An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

Abstract: A system and method for achieving enhanced e-fuse programming reliability. By providing an e-fuse device with redundantly coded fuse structures each with a differing fuse size dimension, reliable encoding of a fuse with a programmed bit is enhanced. That is, for each e-fuse device, each of the multiple fuse structures and a corresponding programming devices associated with each fuse structure is dimensioned to achieve the coding redundancy such that one fuse structure of the multiple fuse structures provides for a current flow of sufficient current density to ensure programming reliability of the e-fuse device. In one embodiment, each the corresponding programming transistor device is of substantially identical size and, each fuse structure of the multiple fuse structures is of a different size. Alternately, each fuse structure is of substantially identical size and each programming transistor device is of a different size, thereby ensuring reliable coding over a programmed current range.

Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.