Abstract: A multi-controller memory system includes a flexible channel memory controller coupled to at least first and second physical interfaces. The second physical interface is also coupled to an auxiliary memory controller. The physical interfaces may be coupled to separate memory modules. In a single-channel control mode, the memory controllers respectively control the memory modules coupled to the first and second physical interface. In a multi-channel control mode, the flexible channel memory controller controls both memory modules while the auxiliary memory controller is inactive. In a single-channel control mode, the memory controllers coordinate restricted memory control commands which access a resource shared by both modules, by one controller transmitting a request signal for the resource to the other controller, awaiting an acknowledgment signal from the other controller, and maintaining transmission of the request signal until the use of the resource is completed.

Abstract: Machine learning based retrieval systems and methods are disclosed for mapping between patent or patent application claims and sections of technical standards Disclosed machine learning-based patent recommender systems may be trained and evaluated on example datasets obtained using the disclosed systems and methods. Systems and methods for generating ground truth datasets associating patent claims and sections of standards from information provided in intellectual property rights (IPR) disclosures or based on user feedback are also disclosed herein.

Abstract: A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.

Abstract: A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.

Abstract: A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.

Abstract: Channel based authentication schemes for intrusion detection that operates at the physical layer are described that apply the capabilities of a pattern reconfigurable antenna for improved performance. Performance gains are achieved by the schemes as a function of the number of antenna modes. The first scheme relies on a channel based fingerprint for differentiating between transmitters whereas another scheme poses the intruder detection problem as a generalized likelihood ratio (GLR) test problem that operates on the channel realizations corresponding to different modes present in a reconfigurable antenna. The benefits of these two schemes over single element antennas are demonstrated. General guidelines are provided on how to choose the different elements of the decision metric in order to realize better performance for physical layer based authentication schemes based on any diversity scheme.

Abstract: A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment's storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.

Abstract: Channel based authentication schemes for intrusion detection that operates at the physical layer are described that apply the capabilities of a pattern reconfigurable antenna for improved performance. Performance gains are achieved by the schemes as a function of the number of antenna modes. The first scheme relies on a channel based fingerprint for differentiating between transmitters whereas another scheme poses the intruder detection problem as a generalized likelihood ratio (GLR) test problem that operates on the channel realizations corresponding to different modes present in a reconfigurable antenna. The benefits of these two schemes over single element antennas are demonstrated. General guidelines are provided on how to choose the different elements of the decision metric in order to realize better performance for physical layer based authentication schemes based on any diversity scheme.

Abstract: Channel based authentication schemes for intrusion detection that operates at the physical layer are described that apply the capabilities of a pattern re-configurable antenna for improved performance. Performance gains are achieved by the schemes as a function of the number of antenna modes. The first scheme relies on a channel based fingerprint for differentiating between transmitters whereas another scheme poses the intruder detection problem as a generalized likelihood ratio (GLR) test problem that operates on the channel realizations corresponding to different modes present in a reconfigurable antenna. The benefits of these two schemes over single element antennas are demonstrated. General guidelines are provided on how to choose the different elements of the decision metric in order to realize better performance for physical layer based authentication schemes based on any diversity scheme.

Abstract: The present invention provides a fastener for securing two pipe adapters within a casing such as a gas turbine casing. The fastener comprises a fastener body having a central bore for receiving the pipe adapters and having a first engagement portion, e.g. a radial projection extending into said central bore, for engagement with a first pipe adapter. The central bore has a second engagement portion, e.g. a threaded portion, for engagement with a second pipe adapter. The fastener further comprises an outer wall at least partly surrounding and spaced from the fastener body in a concentric arrangement. The outer wall comprises a fastener flange extending radially in a direction away from the fastener body for overlaying the casing. At least a portion of the outer wall is deformable (e.g. formed as bellows) so that, in use, axial and/or radial movement of the pipe adapters is dampened.

Abstract: The present invention provides a fastener for securing two pipe adapters within a casing such as a gas turbine casing. The fastener comprises a fastener body having a central bore for receiving the pipe adapters and having a first engagement portion, e.g. a radial projection extending into said central bore, for engagement with a first pipe adapter. The central bore has a second engagement portion, e.g. a threaded portion, for engagement with a second pipe adapter. The fastener further comprises an outer wall at least partly surrounding and spaced from the fastener body in a concentric arrangement. The outer wall comprises a fastener flange extending radially in a direction away from the fastener body for overlaying the casing. At least a portion of the outer wall is deformable (e.g. formed as bellows) so that, in use, axial and/or radial movement of the pipe adapters is dampened.

Abstract: Channel based authentication schemes for intrusion detection that operates at the physical layer are described that apply the capabilities of a pattern re-configurable antenna for improved performance. Performance gains are achieved by the schemes as a function of the number of antenna modes. The first scheme relies on a channel based fingerprint for differentiating between transmitters whereas another scheme poses the intruder detection problem as a generalized likelihood ratio (GLR) test problem that operates on the channel realizations corresponding to different modes present in a reconfigurable antenna. The benefits of these two schemes over single element antennas are demonstrated. General guidelines are provided on how to choose the different elements of the decision metric in order to realize better performance for physical layer based authentication schemes based on any diversity scheme.

Abstract: An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: A medical device having a housing (2) with a bore (3) and a lancet (1) slidably fitting in the bore. The lancet operates as a positive displacement piston. In a retracted position, in which the lancet is rearwardly displaced along the bore to define a fluid-containing space in the bore forwardly on the lancet tip, the fluid-containing space has a cross-section dimension to allow fluid to be retained therein by surface tension. The device has a seal (6) operable substantially to prevent flow of fluid from the fluid-containing space past the seal means on movement of the lancet. Displacement of the lancet between the puncture and retracted positions provides suction for drawing fluid into and along the fluid-containing space from the forward end of the bore, and/or pressure for expelling fluid from the fluid-containing space via the forward end of the bore. Also disclosed are methods for operating the device.

Abstract: An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

Abstract: An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

Abstract: The single use medical device includes a lancet piston slidingly and sealingly located in a bore of a lancet housing. The lancet piston operates as a positive displacement piston within the bore, allowing dispensing and/or aspiration of liquid into the bore. The lancet piston includes a sharp tip for pricking skin, and is particular applicability for allergen testing and blood or ISF sampling. The actuator device has an actuator member for releasable engagement with the lancet piston at a before-use position of the lancet piston via a clutch mechanism. The engagement of the actuator member with the lancet piston allows the actuator member to push/pull the lancet piston forwardly/rearwardly along the bore. At positions forward of the before-use position of the lancet piston, the engagement of the actuator member with the lancet piston is interlocked, assisting in the prevention of accidental needlestick injuries.