Patents by Inventor John McCollum
John McCollum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8320178Abstract: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.Type: GrantFiled: July 1, 2010Date of Patent: November 27, 2012Assignee: Actel CorporationInventor: John McCollum
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Patent number: 8269204Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.Type: GrantFiled: July 1, 2010Date of Patent: September 18, 2012Assignee: Actel CorporationInventors: Jonathan Greene, Frank W. Hawley, John McCollum
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Patent number: 8269203Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.Type: GrantFiled: July 1, 2010Date of Patent: September 18, 2012Assignee: Actel CorporationInventors: Jonathan Greene, Frank W. Hawley, John McCollum
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Patent number: 8258567Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: March 1, 2011Date of Patent: September 4, 2012Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
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Patent number: 8120955Abstract: A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.Type: GrantFiled: February 13, 2009Date of Patent: February 21, 2012Assignee: Actel CorporationInventors: Zhigang Wang, Fethi Dhaoui, John McCollum, Vidyadhara Bellippady
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Publication number: 20110147821Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
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Patent number: 7956404Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: February 13, 2009Date of Patent: June 7, 2011Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7937601Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: GrantFiled: August 5, 2009Date of Patent: May 3, 2011Assignee: Actel CorporationInventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kilkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
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Patent number: 7919977Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.Type: GrantFiled: August 20, 2010Date of Patent: April 5, 2011Assignee: Actel CorporationInventors: Jonathan W. Greene, John McCollum, Volker Hecht
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Patent number: 7915665Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: April 2, 2009Date of Patent: March 29, 2011Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7910436Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.Type: GrantFiled: June 25, 2010Date of Patent: March 22, 2011Assignee: Actel CorporationInventor: John McCollum
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Patent number: 7906805Abstract: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.Type: GrantFiled: August 22, 2008Date of Patent: March 15, 2011Assignee: Actel CorporationInventors: Michael Sadd, Fethi Dhaoui, John McCollum, Richard Chan
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Patent number: 7898018Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: January 26, 2009Date of Patent: March 1, 2011Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
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Patent number: 7884636Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.Type: GrantFiled: July 1, 2010Date of Patent: February 8, 2011Assignee: Actel CorporationInventors: Sana Rezgui, John McCollum, Jih-Jong Wang
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Publication number: 20110024821Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Inventors: Zhigang Wang, Fethi Dhaoui, Michael Sadd, John McCollum, Frank Hawley
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Publication number: 20110018070Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.Type: ApplicationFiled: September 30, 2010Publication date: January 27, 2011Inventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Richard Wilkinson
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Publication number: 20110001108Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
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Publication number: 20110001116Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
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Publication number: 20110002167Abstract: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Inventor: John McCollum
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Publication number: 20110001115Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Inventors: Jonathan Greene, Frank W. Hawley, John McCollum