Abstract: Audio distortion by a speaker may be reduced by detecting onset audio events within an audio signal and modifying the audio to reduce the audio distortion perceived by a listener. The onsets may be detected using a psych-acoustic model by determining critical sub-band powers and corresponding masking thresholds. When a loudness value calculated from the CSBs and masking thresholds exceeds a threshold level, certain frequency bands may be attenuated and other frequency bands may be amplified. The audio modification may be performed on a frame-by-frame basis and each frame may be processed multiple times until the onset is sufficiently masked or attenuated.

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than or equal to 2 and wherein the n-stage stacked charging circuit may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: A thermoelectric conversion device may be made of a pair of dissimilar materials conductively joined at opposite sides, wherein at least one of said materials is a metal ion liquid solution. A thermal differential between the opposite sides creates an electric current flow and the liquid metal ion solution resists thermal equilibrium. The liquid metal ion solution may be contained by a substantially nonconductive material, such as vinyl tubing. A plurality of pairs of these dissimilar materials may be joined in series to increase the current output. The metal ion of the liquid solution may be selected, for example, from a group consisting of Lithium (Li), Sodium (Na), and Potassium (K).

Abstract: A digital filter having improved overload characteristics provides improved performance in audio equalizers and other systems. In contrast to a standard digital filter, clipping is enforced at the output of the filter and an integrator is used to implement the first filter stage, which is then followed by another stage that may be a unit delay or an integrator. Scalers and combiners are provided to scale an input signal representation and the output signal representation and combine them to provide the particular coefficient inputs to the integrator and the second stage forming a direct form filter. The resulting filter implements the same transfer function as a corresponding direct form filter, with an improved recovery from internal overload conditions. Higher-order filters can be formed by cascading the second-order filters formed by multiple integrator/second stage pairs.

Abstract: A simplified digital implementation of a fourth order Linkwitz-Riley crossover network is provided using approximations and transformations of the classical form. The approximation is particularly beneficial when the crossover frequency is low relative to the digital sampling rate, such as when an audio stream is split between bass and treble at about 30-300 Hz and the sampling frequency is about 100 times the cutoff frequency or higher. Rather than merely cascading two sets of second order filters, such as Butterworth filters, a fourth order transfer function is more directly implemented. Conventional transfer functions are simplified through approximations resulting in the elimination of all except one parameter, c, which is a linear function of the cutoff frequency. Additionally, multipliers are moved in line with the integrator elements.

Abstract: A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.

Abstract: A method and system for video-synchronous audio clock generation from an asynchronously sampled video signal provides a mechanism for maintaining synchronization of audio sampling in digital video-audio systems. A ratio between the sampling clock frequency and an audio reference frequency clock is computed via an all digital phase-lock loop (ADPLL) and an audio clock is generated from the ratio by another PLL or a number to clock converter. In systems where a sampling clock to source video clock ratio has been computed for recovering a video signal, the audio ratio can be computed directly from the video ratio.

Abstract: A method and system for surround sound beam-forming using vertically displaced drivers provides a low cost alternative to present external surround array systems. A pair of vertically displaced speaker drivers is supplied with surround and main channel information in a controlled phase relationship with respect to each driver such that the surround channel information is propagated in a directivity pattern substantially differing from that of the main channel information. The main channel information is generally directed at a listening area, while the surround channel information is directed away from the listening area and is substantially attenuated in the direction of the listening area, so that the surround channel information is heard as a diffuse reflected field. An electronic network provides for control of the surround channel phase relationship and combining of main and surround signals for providing inputs to individual power amplifiers for each driver.

Abstract: A method and system for sound beam-forming using internal device speakers in conjunction with external speakers provides a low cost alternative to present external surround array systems. A processing circuit within an audio device or audio/visual (AV) device such as a digital television (DTV) generates signals for internal and external speakers that phase-align the internal speakers with the external speakers for beam-forming. The beam may be a surround beam directed away from a listening position so that surround channel information is only heard as reflections. Alternatively, the beam may be a “night mode” beam that concentrates sound at a particular location or multiple beams may be formed for picture-in-picture or other applications where it is desirable to provide multiple isolated listening locations.

Abstract: A method and system for surround sound beam-forming using the overlapping portion of driver frequency ranges provides a low cost alternative to present external surround array systems. The overlapping frequency range of a pair of speaker drivers, generally a low-frequency and a high-frequency driver, is supplied with a surround channel information in a controlled phase relationship such that the surround channel information is propagated in a directivity pattern substantially differing from that of main channel information supplied to the low and high frequency drivers. The main channel information is generally directed at a listening area, while the surround channel information is directed away from the listening area so that the surround channel information is heard as a diffuse reflected field. An electronic network provides for control of the surround channel phase relationship and combining of main and surround signals via either an active or passive circuit.

Abstract: The quantizers of delta sigma modulators in the signal processing systems described herein use a reduced set of comparators for quantization by predetermining and maintaining a maximum per cycle deviation d between a loop filter output signal VLF(t) and a predicted quantizer output signal qest. In at least one embodiment, a maximum quantizer level deviation d is defined in terms of a number of quantization levels. Thus, the number of comparators in a quantizer needed to quantize the quantizer input signal Vin(t) is based on the maximum quantizer level deviation d. In addition to using fewer comparators than available quantization output levels N, the quantizers can use an even number of comparators M, in contrast to comparable conventional reduced comparator ADC tracking quantizer designs using M+1 number of comparators, where N and M are integers and M<N.

Abstract: Quantizers of delta sigma modulators include comparators to quantize a quantizer input signal. Each comparator compares a respective reference signal to the quantizer input signal. A logic processing module determines a quantizer output signal based upon the comparison. During subsequent periods of time, a comparator offset converter alters “reference signal-to-comparator input terminal” associations to reroute respective reference signals from one arrangement of comparator input terminals of at least two (2) of the comparators to a different arrangement of comparator input terminals. The comparator offset converter can randomly alter the reference signal-to-comparator input terminal associations. The comparator offset converter can maintain a 1:1 reference signal-to-comparator input terminal relationship.

Abstract: A method and apparatus improves the stability and noise performance of frequency synthesis and synchronization circuits. A cancellation circuit provides an error signal that is a measure of integrated quantization error in a delta-sigma modulator that controls the ratiometric division factor in a fractional-N phase-lock loop (PLL). The error signal is fed to the loop filter of the phase-lock loop as a correction signal via a differentiator (high-pass filter). The high pass filter removes substantially all in-band components from the cancellation signal, which reduces the linearity requirement on the cancellation signal path. The cancellation signal can be tapped from an internal numerical integrator of the delta-sigma modulator that is then converted to an analog signal, that is then filtered and combined with the phase comparator output in the loop filter.

Abstract: A delta-sigma modulator circuit with limiter and method provide extended dynamic range in noise-shaped pulse generators. A limiting circuit is provided to adjust the output of the quantizer of the delta-sigma modulator according to a given range of values. The range is adjusted in conformity with a stored previous value of the output of the limiter. The circuit permits adjustment of pulse widths in a consecutive-edge modulator (CEM) to correct conditions where a minimum high-state or low-state pulse width would be violated by the commanded output value of the quantizer. The adjusting circuit delays the rising edge of the next pulse if the minimum low state pulse width would not be met and/or extends the falling edge portion of the next pulse if the minimum high-state pulse width would not be met.

Abstract: A signal processing system includes an analog-to-digital delta sigma modulator with a duty cycle modulator and a finite impulse response (FIR) filter in a main loop feedback path of the delta sigma modulator. The duty cycle modulator and FIR filter can provide high performance filtering in the main loop feedback path. To prevent instability in the main loop caused by the duty cycle modulator and FIR filter, the delta sigma modulator also includes a stabilizer loop. Transfer functions of the main loop and the stabilizer loop combine to achieve a target transfer function for the analog-to-digital delta sigma modulator that provides for stable operation of the analog-to-digital delta sigma modulator.

Abstract: Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample rate. An Infinite Impulse Response filter having internal states are updated at the first sample rate filters the input data samples in, to produce filtered data samples at the first sample rate. Output data samples are output at the second sample rate, where each output data sample is created as the sum of at least two intermediate products, a first intermediate product and a second intermediate product.

Abstract: Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel filter design is used to perform sample rate conversion. The filter may be combined with another digital filter. Two embodiments may be used to achieve this function. In a first embodiment, the filter may be clocked at a first (i.e., input) data rate (i.e., before rate conversion). In a second embodiment, the filter may be clocked at the second (i.e., output) data rate (i.e., after rate conversion). In both cases, the filter's basic structure remains essentially the same, but some extra terms are added to handle the rate conversion. The present application is directed toward a sample-rate conversion filter using the output data rate clock as the filter clock.